path: root/drivers/clk/tegra
AgeCommit message (Expand)Author
2018-08-14Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...Stephen Boyd
2018-08-14Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te...Stephen Boyd
2018-07-25clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver
2018-07-25clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver
2018-07-25clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo
2018-07-08clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko
2018-07-08clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko
2018-07-08clk: tegra: Make vde a child of pll_c3Thierry Reding
2018-07-08clk: tegra: Make vic03 a child of pll_c3Thierry Reding
2018-07-08clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen
2018-06-12treewide: kzalloc() -> kcalloc()Kees Cook
2018-06-04Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and...Stephen Boyd
2018-06-01clk: tegra: no need to check return value of debugfs_create functionsGreg Kroah-Hartman
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko
2018-05-18clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko
2018-05-18clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko
2018-03-12clk: tegra: Fix pll_u rate configurationMarcel Ziswiler
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko
2018-03-12clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko
2018-03-08clk: tegra: MBIST work around for Tegra210Peter De Schrijver
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver
2018-03-08clk: tegra: Add la clock for Tegra210Peter De Schrijver
2017-11-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman
2017-11-01clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen
2017-11-01clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen
2017-11-01clk: tegra: Fix cclk_lp divisor registerMichał Mirosław
2017-11-01clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko
2017-11-01clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko
2017-11-01clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko
2017-11-01clk: tegra: Mark APB clock as criticalJon Hunter
2017-10-19clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal
2017-10-19clk: tegra: Fix sor1_out clock implementationThierry Reding
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding
2017-10-19clk: tegra: Add peripheral clock registration helperThierry Reding
2017-10-19clk: tegra: Check BPMP response return codeTimo Alho
2017-08-23clk: tegra: Fix Tegra210 PLLU initializationAlex Frid
2017-08-23clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid
2017-08-23clk: tegra: Fix T210 PLLRE registrationAlex Frid
2017-08-23clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid
2017-08-23clk: tegra: Re-factor T210 PLLX registrationAlex Frid
2017-08-23clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver
2017-08-23clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver
2017-08-23clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid
2017-08-23clk: tegra: Fix T210 effective NDIV calculationAlex Frid
2017-08-23clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver
2017-08-23clk: tegra210: remove non-existing VFIR clockPeter De Schrijver