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path: root/drivers/clk/tegra/clk.h
AgeCommit message (Expand)Author
2018-07-25clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver
2018-07-25clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver
2017-10-19clk: tegra: Add peripheral clock registration helperThierry Reding
2017-08-23clk: tegra: Re-factor T210 PLLX registrationAlex Frid
2017-03-20clk: tegra: Fix build warnings on Tegra20/Tegra30Thierry Reding
2017-03-20clk: tegra: Add super clock mux/dividerPeter De Schrijver
2017-03-20clk: tegra: Fix constness for peripheral clocksPeter De Schrijver
2017-03-20clk: tegra: Fix type for m fieldPeter De Schrijver
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein
2016-04-28clk: tegra: Add fixed factor peripheral clock typeThierry Reding
2016-04-28clk: tegra: Constify peripheral clock registersThierry Reding
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein
2015-12-17clk: tegra: Add Super Gen5 LogicBill Huang
2015-12-17clk: tegra: pll: Add logic for SSBill Huang
2015-12-17clk: tegra: pll: Add dyn_ramp callbackRhyland Klein
2015-12-17clk: tegra: pll: Add Set_default logicBill Huang
2015-12-17clk: tegra: pll: Adjust vco_min if SDM presentBill Huang
2015-12-17clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein
2015-12-17clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein
2015-11-20clk: tegra: pll: Add code to handle if resets are supported by PLLBill Huang
2015-11-20clk: tegra: pll: Add logic for out-of-table rates for T210Rhyland Klein
2015-11-20clk: tegra: pll: Add logic for handling SDM dataRhyland Klein
2015-11-20clk: tegra: pll: Change misc_reg count from 3 to 6Bill Huang
2015-11-20clk: tegra: pll: Add tegra_pll_wait_for_lock to clk headerRhyland Klein
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein
2015-10-20clk: tegra: Update struct tegra_clk_pll_params kerneldocThierry Reding
2015-10-20clk: tegra: Fix comments for structure definitionsRhyland Klein
2015-07-16clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen
2015-05-13clk: tegra: EMC clock driver depends on EMC driverThierry Reding
2015-05-13clk: tegra: Add EMC clock driverMikko Perttunen
2015-04-10clk: tegra: Model oscillator as clockThierry Reding
2015-04-10clk: tegra: Fix typo tabel -> tableThierry Reding
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding
2013-12-11clk: tegra: remove legacy reset APIsStephen Warren
2013-12-11clk: tegra: implement a reset driverStephen Warren
2013-11-26clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver
2013-11-26clk: tegra: add locking to periph clksPeter De Schrijver
2013-11-26clk: tegra: Add support for PLLSSPeter De Schrijver
2013-11-26clk: tegra: introduce common gen4 super clockPeter De Schrijver
2013-11-26clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver
2013-11-26clk: tegra: move audio clk to common filePeter De Schrijver
2013-11-26clk: tegra: add clkdev registration infraPeter De Schrijver
2013-11-26clk: tegra: add common infra for DT clocksPeter De Schrijver
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver