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path: root/drivers/clk/tegra/clk-tegra124.c
AgeCommit message (Expand)Author
2020-05-12clk: tegra: Fix initial rate for pll_a on Tegra124Thierry Reding
2020-03-12clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni
2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni
2020-03-12clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni
2020-03-12clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni
2020-03-12clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni
2019-11-11clk: tegra: Reimplement SOR clock on Tegra124Thierry Reding
2019-11-11clk: tegra: Rename sor0_lvds to sor0_outThierry Reding
2019-11-11clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd
2019-04-25clk: tegra124: Remove lock-enable bit from PLLMDmitry Osipenko
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski
2018-12-14clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter
2018-07-08clk: tegra: Make vde a child of pll_c3Thierry Reding
2018-07-08clk: tegra: Make vic03 a child of pll_c3Thierry Reding
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker
2016-04-28clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding
2015-11-18clk: tegra: Format tables consistentlyThierry Reding
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding
2015-11-18clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein
2015-08-25clk: tegra: Fix some static checker problemsStephen Boyd
2015-08-25Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd
2015-07-20clk: tegra: Properly include clk.hStephen Boyd
2015-07-16clk: tegra: Save/restore CCLKG_BURST_POLICY on suspendTuomas Tynkkynen
2015-07-16clk: tegra: Add DFLL DVCO reset control for Tegra124Paul Walmsley
2015-05-13clk: tegra: Set the EMC clock as the parent of the MC clockTomeu Vizoso
2015-05-13clk: tegra: Add EMC clock driverMikko Perttunen
2015-05-13clk: tegra: Remove old Tegra124 EMC clockMikko Perttunen
2015-04-10clk: tegra: Use the proper parent for plld_dsiThierry Reding
2015-04-10clk: tegra: Model oscillator as clockThierry Reding
2015-04-10clk: tegra: Enable HDA to HDMI clocks on Tegra124Dylan Reid
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang
2015-02-02clk: tegra: Add support for the Tegra132 CAR IP blockPaul Walmsley
2015-02-02clk: tegra124: Add init data for dsi lp clocksSean Paul
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding
2014-09-18clk: tegra124: Add PLL_M_UD and PLL_C_UD clocksMikko Perttunen
2014-06-27clk: tegra124: init table updatesPeter De Schrijver
2014-06-25clk: tegra: Add SATA clocks to Tegra124 initialization tableMikko Perttunen
2014-06-25clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver
2014-05-22clk: tegra: Initialize xusb clocksAndrew Bresticker
2014-05-22clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker