path: root/arch/x86/events
AgeCommit message (Expand)Author
2020-03-31Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/k...Linus Torvalds
2020-03-25Merge branch 'x86/cpu' into perf/core, to resolve conflictIngo Molnar
2020-03-24x86/perf/events: Convert to new CPU match macrosThomas Gleixner
2020-03-20perf/x86/intel/uncore: Factor out __snr_uncore_mmio_init_boxKan Liang
2020-03-20perf/x86/intel/uncore: Add box_offsets for free-running countersKan Liang
2020-03-19Merge branch 'perf/urgent' into perf/core, to pick up fixesIngo Molnar
2020-03-17perf/amd/uncore: Add support for Family 19h L3 PMUKim Phillips
2020-03-17perf/amd/uncore: Make L3 thread mask code more readableKim Phillips
2020-03-17perf/amd/uncore: Prepare L3 thread mask code for Family 19hKim Phillips
2020-03-12perf/amd/uncore: Replace manual sampling check with CAP_NO_INTERRUPT flagKim Phillips
2020-02-15x86 user stack frame reads: switch to explicit __get_user()Al Viro
2020-02-11perf/x86: Add Intel Tiger Lake uncore supportKan Liang
2020-02-11perf/x86/intel: Output LBR TOS information correctlyKan Liang
2020-02-11perf/core: Add new branch sample type for HW index of raw branch recordsKan Liang
2020-02-11perf/x86/intel: Avoid unnecessary PEBS_ENABLE MSR access in PMIKan Liang
2020-02-11perf/x86/intel: Fix inaccurate period in context switch for auto-reloadKan Liang
2020-02-11perf/x86/amd: Add missing L2 misses event spec to AMD Family 17h's event mapKim Phillips
2020-02-11perf/x86/msr: Add Tremont supportKan Liang
2020-02-11perf/x86/cstate: Add Tremont supportKan Liang
2020-02-11perf/x86/intel: Add Elkhart Lake supportKan Liang
2020-01-28Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kern...Linus Torvalds
2020-01-28Merge branch 'core-headers-for-linus' of git://git.kernel.org/pub/scm/linux/k...Linus Torvalds
2020-01-20Merge tag 'v5.5-rc7' into perf/core, to pick up fixesIngo Molnar
2020-01-17perf/x86/intel/uncore: Remove PCIe3 unit for SNRKan Liang
2020-01-17perf/x86/intel/uncore: Fix missing marker for snr_uncore_imc_freerunning_eventsKan Liang
2020-01-17perf/x86/intel/uncore: Add PCI ID of IMC for Xeon E3 V5 FamilyKan Liang
2020-01-17perf/x86/amd: Add support for Large Increment per Cycle EventsKim Phillips
2020-01-17perf/x86/amd: Constrain Large Increment per Cycle eventsKim Phillips
2020-01-17perf/x86/intel/rapl: Add Comet Lake supportHarry Pan
2019-12-17perf/x86/intel: Fix PT PMI handlingAlexander Shishkin
2019-12-17perf/x86/intel/bts: Fix the use of page_private()Alexander Shishkin
2019-12-17perf/x86: Fix potential out-of-bounds accessPeter Zijlstra
2019-12-10perf/x86/intel: Explicitly include asm/io.h to use virt_to_phys()Sean Christopherson
2019-11-27perf/x86: Implement immediate enforcement of /sys/devices/cpu/rdpmc value of 0Anthony Steinhauser
2019-11-26Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kern...Linus Torvalds
2019-11-21Merge branch 'kvm-tsx-ctrl' into HEADPaolo Bonzini
2019-11-15x86: retpolines: eliminate retpoline from msr event handlersAndrea Arcangeli
2019-11-13perf/x86/intel/pt: Prevent redundant WRMSRsAlexander Shishkin
2019-11-13perf/x86/intel/pt: Opportunistically use single range output modeAlexander Shishkin
2019-11-13perf/x86/intel/pt: Add sampling supportAlexander Shishkin
2019-11-13perf/x86/intel/pt: Factor out pt_config_start()Alexander Shishkin
2019-11-11perf/x86/amd: Remove set but not used variable 'active'Zheng Yongjun
2019-10-28perf/x86: Synchronize PMU task contexts on optimized context switchesAlexey Budankov
2019-10-28perf/x86/intel: Implement LBR callstack context synchronizationAlexey Budankov
2019-10-28perf/x86: Install platform specific ->swap_task_ctx() adapterAlexey Budankov
2019-10-28perf/core, perf/x86: Introduce swap_task_ctx() method at 'struct pmu'Alexey Budankov
2019-10-28Merge branch 'perf/urgent' into perf/core, to pick up fixesIngo Molnar
2019-10-28perf/x86/uncore: Fix event group supportKan Liang
2019-10-28perf/x86/amd/ibs: Handle erratum #420 only on the affected CPU family (10h)Kim Phillips
2019-10-28perf/x86/amd/ibs: Fix reading of the IBS OpData register and thus precise RIP...Kim Phillips