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authorRalf Baechle <ralf@linux-mips.org>2005-09-03 15:56:17 -0700
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 00:06:07 -0700
commit42a3b4f25af8f8d77feddf27f839fa0628dbff1a (patch)
tree332370ff3889fabb66a45fb5dcf605b142de77c8 /include/asm-mips/war.h
parent875d43e72b5bf22161a81de7554f88eccf8a51ae (diff)
downloadlinux-stericsson-42a3b4f25af8f8d77feddf27f839fa0628dbff1a.tar.gz
[PATCH] mips: nuke trailing whitespace
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-mips/war.h')
-rw-r--r--include/asm-mips/war.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index c4a704121343..04ee53b34c2e 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -113,7 +113,7 @@
*/
#define BCM1250_M3_WAR 1
-/*
+/*
* This is a DUART workaround related to glitches around register accesses
*/
#define SIBYTE_1956_WAR 1
@@ -122,7 +122,7 @@
/*
* Fill buffers not flushed on CACHE instructions
- *
+ *
* Hit_Invalidate_I cacheops invalidate an icache line but the refill
* for that line can get stale data from the fill buffer instead of
* accessing memory if the previous icache miss was also to that line.