path: root/drivers
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authorStephen Boyd <sboyd@kernel.org>2018-08-14 22:58:39 -0700
committerStephen Boyd <sboyd@kernel.org>2018-08-14 22:58:39 -0700
commitea4f7872c71adef8897f71bb6bb056856ccc8ed9 (patch)
tree61658737767f6f7ca4830b2bc2f8126a061e7458 /drivers
parentb183c6887af3bba1835bd4c9ef2de119afab737b (diff)
parent2b555a4b9caecfcab1b2aade176df795ceceaefa (diff)
parent33f5104624b96c6514621e63909b5703276b4dac (diff)
parentfc20654389364a55eeab837244b24f8da75009f6 (diff)
parentcd88259a7215e0737f8ef2c2842f41922ae87d8d (diff)
parent9d8108f9f3cb996a9677223fcd1feeb1f3e05566 (diff)
Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next
* clk-ingenic-fixes: : - Ingenic i2s bit update and allow UDC clk to gate clk: ingenic: Add missing flag for UDC clock clk: ingenic: Fix incorrect data for the i2s clock * clk-max9485: : - Maxim 9485 Programmable Clock Generator clk: Add driver for MAX9485 dts: clk: add devicetree bindings for MAX9485 * clk-pxa-32k-pll: : - Expose 32 kHz PLL on PXA SoCs clk: pxa: export 32kHz PLL * clk-aspeed: : - Fix name of aspeed SDC clk define to have only one 'CLK' clk: aspeed: Fix SDCLK name * clk-imx6sll-gpio: : - imx6sll GPIO clk gate support clk: imx6sll: add GPIO LPCGs