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authorThierry Reding <treding@nvidia.com>2018-06-11 10:18:53 +0200
committerStephen Boyd <sboyd@kernel.org>2018-07-08 17:03:59 -0700
commit26f8590c4a1f7bd30ef9b9d713388bd96eb43d16 (patch)
tree4ad85c8ec1f234365eaa616101a300ef50c3a8af /drivers
parentce397d215ccd07b8ae3f71db689aedb85d56ab40 (diff)
downloadlinux-stericsson-26f8590c4a1f7bd30ef9b9d713388bd96eb43d16.tar.gz
clk: tegra: Make vic03 a child of pll_c3
By default, the vic03 clock is a child of pll_m but that runs at 924 MHz which is too fast for VIC. Make vic03 a child of pll_c3 by default so it will run at a supported frequency. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/tegra/clk-tegra124.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 0c69c7970950..f5048f82c0b9 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
{ TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
+ { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },
/* must be the last entry */
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
};