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authorAlex Deucher <alexander.deucher@amd.com>2014-08-19 11:48:30 -0400
committerAlex Deucher <alexander.deucher@amd.com>2014-08-19 11:48:30 -0400
commitcd1c9c1a4b06d3bc264e774ad84c410ce02e124e (patch)
tree8c0c3202077a03882cc534530cd978a4a1fcd738 /drivers/gpu/drm
parent86302eeadebfab94530b00f5e53a23f911ff41e4 (diff)
downloadlinux-stericsson-cd1c9c1a4b06d3bc264e774ad84c410ce02e124e.tar.gz
drm/radeon: re-enable selective GPUVM flushing
Now that the PFP and ME synchronization is fixed, we can enable this again reliably. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/radeon/radeon_vm.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index 832ef320c26d..088ffdc2f577 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -238,9 +238,7 @@ void radeon_vm_flush(struct radeon_device *rdev,
uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
/* if we can't remember our last VM flush then flush now! */
- /* XXX figure out why we have to flush all the time before CIK */
- if (rdev->family < CHIP_BONAIRE ||
- !vm->last_flush || pd_addr != vm->pd_gpu_addr) {
+ if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
trace_radeon_vm_flush(pd_addr, ring, vm->id);
vm->pd_gpu_addr = pd_addr;
radeon_ring_vm_flush(rdev, ring, vm);