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authorMichel Dänzer <michel.daenzer@amd.com>2014-07-31 18:43:49 +0900
committerAlex Deucher <alexander.deucher@amd.com>2014-08-05 08:53:45 -0400
commit72a9987edcedb89db988079a03c9b9c65b6ec9ac (patch)
tree80fb28570b7cf060188bdad013f0aa58b4a25fb0 /drivers/gpu/drm/radeon/radeon_drv.c
parent124764f17473479061942429ada2e5e786d5d6ed (diff)
downloadlinux-stericsson-72a9987edcedb89db988079a03c9b9c65b6ec9ac.tar.gz
drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it safe: * For userspace to stream data from CPU to GPU via VRAM instead of GTT * For IBs to be stored in VRAM instead of GTT * For ring buffers to be stored in VRAM instead of GTT, if the HPD flush is performed via MMIO Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_drv.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index e9e361084249..54aa293a8175 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -82,9 +82,11 @@
* 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
* CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
* 2.39.0 - Add INFO query for number of active CUs
+ * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
+ * CS to GPU
*/
#define KMS_DRIVER_MAJOR 2
-#define KMS_DRIVER_MINOR 39
+#define KMS_DRIVER_MINOR 40
#define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev);