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authorMichel Dänzer <michel.daenzer@amd.com>2014-07-31 18:43:49 +0900
committerAlex Deucher <alexander.deucher@amd.com>2014-08-05 08:53:45 -0400
commit72a9987edcedb89db988079a03c9b9c65b6ec9ac (patch)
tree80fb28570b7cf060188bdad013f0aa58b4a25fb0 /drivers/gpu/drm/radeon/radeon.h
parent124764f17473479061942429ada2e5e786d5d6ed (diff)
downloadlinux-stericsson-72a9987edcedb89db988079a03c9b9c65b6ec9ac.tar.gz
drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it safe: * For userspace to stream data from CPU to GPU via VRAM instead of GTT * For IBs to be stored in VRAM instead of GTT * For ring buffers to be stored in VRAM instead of GTT, if the HPD flush is performed via MMIO Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index bcc98c1c135e..29731584b6ae 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1749,6 +1749,7 @@ struct radeon_asic_ring {
/* command emmit functions */
void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
+ void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
struct radeon_semaphore *semaphore, bool emit_wait);
void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);