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authorAkshu Agrawal <akshu.agrawal@amd.com>2018-08-21 12:21:57 +0530
committerStephen Boyd <sboyd@kernel.org>2018-08-30 14:47:41 -0700
commitbded6c03e398dc6e862dc8301fb9a60175740653 (patch)
tree76e234ab9e899808d5bd2f5b492f9585354a0aba /drivers/clk/x86/clk-st.c
parent450b6b9b169382205f88858541a8b79830262ce7 (diff)
downloadlinux-stericsson-bded6c03e398dc6e862dc8301fb9a60175740653.tar.gz
clk: x86: Set default parent to 48Mhz
System clk provided in ST soc can be set to: 48Mhz, non-spread 25Mhz, spread To get accurate rate, we need it to set it at non-spread option which is 48Mhz. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Fixes: 421bf6a1f061 ("clk: x86: Add ST oscout platform clock") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/x86/clk-st.c')
-rw-r--r--drivers/clk/x86/clk-st.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-st.c
index fb62f3938008..3a0996f2d556 100644
--- a/drivers/clk/x86/clk-st.c
+++ b/drivers/clk/x86/clk-st.c
@@ -46,7 +46,7 @@ static int st_clk_probe(struct platform_device *pdev)
clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
- clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk);
+ clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
0, st_data->base + MISCCLKCNTL1, OSCCLKENB,