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authorPeter De Schrijver <pdeschrijver@nvidia.com>2018-07-12 14:53:00 +0300
committerStephen Boyd <sboyd@kernel.org>2018-07-25 13:43:34 -0700
commitcb3ac5947afb3bb7e2f89c1b59f61dcf3e115fe1 (patch)
tree7111e58446fef9a299069b9104c9e32a09732a11 /drivers/clk/tegra/clk.h
parent0cbb61a313979b53d6b2dc838a92f07471440708 (diff)
downloadlinux-stericsson-cb3ac5947afb3bb7e2f89c1b59f61dcf3e115fe1.tar.gz
clk: tegra: Refactor fractional divider calculation
Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
-rw-r--r--drivers/clk/tegra/clk.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e3b9c22ad8b2..c733841aa6db 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -812,6 +812,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
+int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
+ u8 frac_width, u8 flags);
+
/* Combined read fence with delay */
#define fence_udelay(delay, reg) \