path: root/drivers/clk/tegra/clk-divider.c
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authorStephen Boyd <sboyd@kernel.org>2018-08-14 22:58:53 -0700
committerStephen Boyd <sboyd@kernel.org>2018-08-14 22:58:53 -0700
commit032405a754fb338812732eac449cd10173f13a1a (patch)
tree88c9f4e4c56c2690cace58b6901e5bf842c3e2fb /drivers/clk/tegra/clk-divider.c
parent4a18ef5babd1bac0c746e87d1b94a7696fcd36be (diff)
parentd7b7c00dad79f7cc78dac87a3ff2f06358518384 (diff)
parent7f5eac5934d747535f9ffc997792a0a6eb289374 (diff)
parentc76a69e477b88f259bcc118129874011abcaae86 (diff)
parentcec5dfa4e49c62e3e662a98abdba631422a76b82 (diff)
parentff388ee3651642d7fdc837b4434a1c7d80b243e4 (diff)
Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next
* clk-imx6-ocram: : - i.MX6SX ocram_s clk support clk: imx: add ocram_s clock for i.mx6sx * clk-missing-put: : - Add missing of_node_put()s in some i.MX clk drivers clk: imx6sll: fix missing of_node_put() clk: imx6ul: fix missing of_node_put() * clk-tegra-sdmmc-jitter: : - Tegra SDMMC clk jitter improvements with high speed signaling modes clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks clk: tegra: Add sdmmc mux divider clock clk: tegra: Refactor fractional divider calculation clk: tegra: Fix includes required by fence_udelay() * clk-allwinner: clk: sunxi-ng: add A64 compatible string dt-bindings: add compatible string for the A64 DE2 CCU clk: sunxi-ng: r40: Export video PLLs clk: sunxi-ng: r40: Allow setting parent rate to display related clocks clk: sunxi-ng: r40: Add minimal rate for video PLLs * clk-uniphier: : - Uniphier NAND, USB3 PHY, and SPI clk support clk: uniphier: add clock frequency support for SPI clk: uniphier: add more USB3 PHY clocks clk: uniphier: add NAND 200MHz clock