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authorElizabeth Oldham <beth@mips.com>2006-08-17 12:39:21 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-09-27 13:37:36 +0100
commita94d702049569401c65b579d0751ce282f962b41 (patch)
tree4272d85203da3648ef1f6feea02c24465e132057 /arch/mips/kernel/vpe.c
parent6e74bae9a0c2fc59ffb0e25fec074b4ac0ac7048 (diff)
downloadlinux-stericsson-a94d702049569401c65b579d0751ce282f962b41.tar.gz
[MIPS] MT: Fix setting of XTC.
XTC can only be set if VPA is clear, which it may not be. There is also the possibility of a back to back c0 register access hazard to take care of. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/vpe.c')
-rw-r--r--arch/mips/kernel/vpe.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 9ee0ec2cd067..51ddd2166898 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -768,10 +768,16 @@ int vpe_run(struct vpe * v)
*/
write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | v->minor);
+ write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA));
+
+ back_to_back_c0_hazard();
+
/* Set up the XTC bit in vpeconf0 to point at our tc */
write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))
| (t->index << VPECONF0_XTC_SHIFT));
+ back_to_back_c0_hazard();
+
/* enable this VPE */
write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);