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SPC controller driver has already populated frequency table from firmware and
not its time to share it with other frameworks like: cpufreq. This patch
provides interface to get freq table from spc driver.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Not only the pointed data, but the pointer as well has to be flushed
out of the cache.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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vexpress_spc_check_loaded()
Even if it is initialized via early_INITCALL(), there are other pieces
of code that also have to be initialized with early_initcall() and
the relative call ordering may not always be satisfied.
So try to initialize the SPC code when vexpress_spc_check_loaded() is
called if that has not been done yet.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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Both SPC OPP and COMMS request takes ~3-5ms at max with CPU
wakeup enabled. The OPP change takes ~900us and COMMS ~200us if
wakeup are disabled. Since all the operations are serialised in the
firmware and CA7 wakeup takes ~2ms max, this could affect other SPC
request when they occur at the same time.
Further an SPC request could start just before jiffie is about to be
updated. In order to handle any of these cases, this patch changes
timeout value to 20ms.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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The latest firmware has the following protocol for PWC_STATUS update
to communicate status/faults:
CA15 DVFS request: 0x0001 complete, 0x0002 error
CA7 DVFS request: 0x0010 complete, 0x0020 error
SPC_SYS_CFG request: 0x0100 complete, 0x0200 error
This patch updates the driver to handle the error conditions based on
the above protocol.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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This patch changes the input parameter of spc_get/spc_set_perf
routines to frequency instead of performance index as expected
by the firmware. The SPC driver now has the list of frequencies
supported by the firmware, so it can map the requested frequency
to the right performance index.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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This patch adds support to read the SPC virtual registers that store
the OPPs through SYS_CFG interface. This helps in avoiding to rely on
DT for frequency to performanace index as expected by firmware.
It can also be used to get other information from the firware.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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In order to compare the given cluster id with A15, the A15_CONF is read
everytime. Instead read the A15 cluster id once during initialisation
and store the same for all future references.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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The SCC/SPC offsets defined in spc driver are scattered a bit.
Just reordering them for better readability.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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This patch initializes the SPC driver before smp initialization is done.
The driver is required to be able to use the power api to bring up
secondary cpus. Hence its availability is mandatory at this stage.
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This patch ensures that the SPC registers written by the power api
are read back to ensure that the changes have reflected. This is
done to workaround any delays caused by the slow nature of the SPC
interface e.g. the wfi signal being asserted to the SPC before the
changes to the SPC registers have taken effect.
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Otherwise any concurrent call could reset the completion block
while it is being waited for by a previous call.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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Picked wholesale in the IKS tree from ARM.
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Non-local variables used by the CCI and SPC management functions
called by tc2_pm_power_down() after disabling the cache must be
flushed out to main memory in advance, otherwise incoherency of
those values may occur if they are sitting in the cache of some
other CPU when tc2_pm_power_down() executes.
This patch adds the appropriate flushing to the CCI and SPC drivers
to ensure that the relevant data is available in RAM ahead of time.
Because this creates a dependency on arch-specific cacheflushing
functions, this patch also makes ARM_CCI and ARM_SPC depend on ARM
(pending a proper tidyup of those drivers).
Signed-off-by: Dave Martin <dave.martin@linaro.org>
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To enable drivers which use SPC functions to safely exist in kernels
which are run on hardware without SPC hardware, they need a method of
detecting its presence. The new function vexpress_spc_check_loaded()
provides this.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The TC2 core tile integrates a logic block that provides the interface
between the dual cluster test-chip and the M3 microcontroller that carries
out power management. The logic block, called SPC, contains several
memory mapped registers to control among other things low-power states,
operating points and reset control.
This patch provides a driver that enables run-time control of features
implemented by the SPC control logic.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
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This patch provides the new kernel infrastructure needed by versatile
express boards. Drivers are moved to drivers/misc/vexpress directory,
where Kconfig and Makefile are created. A coalesced include file is
created to cater for all versatile express required function declarations.
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