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authorLen Brown <len.brown@intel.com>2013-02-02 01:31:56 -0500
committerLen Brown <len.brown@intel.com>2013-02-13 18:22:08 -0500
commit32e9518005c8dd9ed668f40f98632c8186df4909 (patch)
tree277dde14dec62b8734d404f74f55335ce354d43f /tools
parente022e7eb90f3edb83f9ff77825eda3d1b3a2f2e0 (diff)
downloadvexpress-lsk-32e9518005c8dd9ed668f40f98632c8186df4909.tar.gz
intel_idle: export both C1 and C1E
Here we disable HW promotion of C1 to C1E and export both C1 and C1E and distinct C-states. This allows a cpuidle governor to choose a lower latency C-state than C1E when necessary to satisfy performance and QOS constraints -- and still save power versus polling. This also corrects the erroneous latency previously reported for C1E -- it is 10usec, not 1usec. Note that if you use "intel_idle.max_cstate=N", then you must increment N by 1 to get the same behavior after this change. Signed-off-by: Len Brown <len.brown@intel.com>
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