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authorJens Renner \(EFE\) <renner@efe-gmbh.de>2013-06-03 04:32:52 +0000
committerDavid S. Miller <davem@davemloft.net>2013-06-04 17:21:28 -0700
commit3a5395b3d57b9e3836c755434c88f4590d5ea6f6 (patch)
tree3243e630dea95d247e4538801df4cbf67257b7a9 /drivers/net/ethernet
parent44dbc78ee43d5df0bbcd7f3ae6a0ba00ed261e95 (diff)
downloadvexpress-lsk-3a5395b3d57b9e3836c755434c88f4590d5ea6f6.tar.gz
net: ethernet: xilinx_emaclite: set protocol selector bits when writing ANAR
This patch sets the protocol selector bits (4:0) of the PHY's MII_ADVERTISE register (ANAR) when writing ADVERTISE_ALL. The protocol selector bits are indicating IEEE 803.3u support and are fixed / read-only on some PHYs. Not setting them correctly on others (like TI DP83630) makes the PHY fall back to 10M HDX mode which should be avoided. Tested for TI DP83630 PHY on Microblaze platform. Signed-off-by: Jens Renner <renner@efe-gmbh.de> Tested-by: Michal Simek <monstr@monstr.eu> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r--drivers/net/ethernet/xilinx/xilinx_emaclite.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 919b983114e..b7268b3dae7 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -946,7 +946,8 @@ static int xemaclite_open(struct net_device *dev)
phy_write(lp->phy_dev, MII_CTRL1000, 0);
/* Advertise only 10 and 100mbps full/half duplex speeds */
- phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL);
+ phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL |
+ ADVERTISE_CSMA);
/* Restart auto negotiation */
bmcr = phy_read(lp->phy_dev, MII_BMCR);