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authorNithin Sujir <nsujir@broadcom.com>2013-04-09 08:48:07 +0000
committerDavid S. Miller <davem@davemloft.net>2013-04-09 15:14:14 -0400
commit942d1af00a28aa760ffad970e181b386cbda322a (patch)
treec101e8958ce35bd60d47f6063d5a799545fb289d /drivers/net/ethernet/broadcom/tg3.h
parent85730a631f0c9fadcf0cc9587cacc755f50766fa (diff)
downloadvexpress-lsk-942d1af00a28aa760ffad970e181b386cbda322a.tar.gz
tg3: Add support for link flap avoidance
This patch and the following two patches add support for link flap avoidance by maintaining the link on power down. This feature is required for management capable devices to have the management connection uninterrupted on driver reload, reboot and interface up/down. The other pros of this feature are - It speeds up boot up time by several seconds as DHCP addresses can be acquired faster. - It avoids lengthy Spanning Tree delay. On powerup the hardware brings up the phy with default settings. If the link is not up, the management software configures the phy to gigabit and starts autonegotiate. Subsequently, as long as the link is up, the driver and management refrain from resetting and/or changing any configuration that the link depends on. The LNK_FLAP_AVOID setting is an NVRAM user configurable bit and is disabled by default. If this setting is enabled, we skip powering down the phy and resetting it. A second NVRAM setting is 1G_ON_VAUX_OK (off by default). This adds support for gigabit link speed when device is on auxiliary power. Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/tg3.h')
-rw-r--r--drivers/net/ethernet/broadcom/tg3.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index fd00a38b7ab..150bfc71c39 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -2198,6 +2198,8 @@
#define NIC_SRAM_DATA_CFG_3 0x00000d3c
#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
+#define NIC_SRAM_LNK_FLAP_AVOID 0x00400000
+#define NIC_SRAM_1G_ON_VAUX_OK 0x00800000
#define NIC_SRAM_DATA_CFG_4 0x00000d60
#define NIC_SRAM_GMII_MODE 0x00000002
@@ -3305,6 +3307,8 @@ struct tg3 {
#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
#define TG3_PHYFLG_EEE_CAP 0x00040000
+#define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000
+#define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000
#define TG3_PHYFLG_MDIX_STATE 0x00200000
u32 led_ctrl;