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authorMichael Neuling <michael.neuling@au1.ibm.com>2013-04-24 00:30:09 +0000
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-05-07 20:33:03 -0700
commitefaa9d79ccb5491181ea100dc6a9c575f626ef5a (patch)
treeb24864edeee013e7b3c413d813df66b00a7a9f61 /arch
parent3e33f340b72643250afe21f8a0fc5b90f543a169 (diff)
downloadvexpress-lsk-efaa9d79ccb5491181ea100dc6a9c575f626ef5a.tar.gz
powerpc: Add isync to copy_and_flush
commit 29ce3c5073057991217916abc25628e906911757 upstream. In __after_prom_start we copy the kernel down to zero in two calls to copy_and_flush. After the first call (copy from 0 to copy_to_here:) we jump to the newly copied code soon after. Unfortunately there's no isync between the copy of this code and the jump to it. Hence it's possible that stale instructions could still be in the icache or pipeline before we branch to it. We've seen this on real machines and it's results in no console output after: calling quiesce... returning from prom_init The below adds an isync to ensure that the copy and flushing has completed before any branching to the new instructions occurs. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/kernel/head_64.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 0886ae6dd5b..b61363d557b 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -509,6 +509,7 @@ _GLOBAL(copy_and_flush)
sync
addi r5,r5,8
addi r6,r6,8
+ isync
blr
.align 8