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authorGavin Shan <shangw@linux.vnet.ibm.com>2012-08-20 03:49:15 +0000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-09-17 16:35:13 +1000
commit7ebdf956df7961ae6b57b0328e03d33f95f1346f (patch)
tree6805625c08e697e3d1c2369ae3f9e0ee60a17904 /arch/powerpc/platforms/powernv/pci.h
parentfb446ad075cfa5212b26c4f77751faefe574ad8b (diff)
downloadvexpress-lsk-7ebdf956df7961ae6b57b0328e03d33f95f1346f.tar.gz
powerpc/powernv: PE list based on creation order
The resource (I/O and MMIO) will be assigned on basis of PE from top to bottom so that we can implement the trick here: the resource that has been assigned to parent PE could be taken by child PE if necessary. The current implementation already has PE list per PHB basis, but the list doesn't meet our requirment: tracing PE based on their cration time from top to bottom. So the patch does rename for the DMA based PE list and introduces the list to trace the PEs sequentially based on their creation time. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Reviewed-by: Ram Pai <linuxram@us.ibm.com> Reviewed-by: Richard Yang <weiyang@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/platforms/powernv/pci.h')
-rw-r--r--arch/powerpc/platforms/powernv/pci.h20
1 files changed, 13 insertions, 7 deletions
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 8bc47963464..b70720bd943 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -17,9 +17,14 @@ enum pnv_phb_model {
};
#define PNV_PCI_DIAG_BUF_SIZE 4096
+#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
+#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
+#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_ioda_pe {
+ unsigned long flags;
+
/* A PE can be associated with a single device or an
* entire bus (& children). In the former case, pdev
* is populated, in the later case, pbus is.
@@ -40,11 +45,6 @@ struct pnv_ioda_pe {
*/
unsigned int dma_weight;
- /* This is a PCI-E -> PCI-X bridge, this points to the
- * corresponding bus PE
- */
- struct pnv_ioda_pe *bus_pe;
-
/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
int tce32_seg;
int tce32_segcount;
@@ -59,7 +59,8 @@ struct pnv_ioda_pe {
int mve_number;
/* Link in list of PE#s */
- struct list_head link;
+ struct list_head dma_link;
+ struct list_head list;
};
struct pnv_phb {
@@ -107,6 +108,11 @@ struct pnv_phb {
unsigned int *io_segmap;
struct pnv_ioda_pe *pe_array;
+ /* Sorted list of used PE's based
+ * on the sequence of creation
+ */
+ struct list_head pe_list;
+
/* Reverse map of PEs, will have to extend if
* we are to support more than 256 PEs, indexed
* bus { bus, devfn }
@@ -125,7 +131,7 @@ struct pnv_phb {
/* Sorted list of used PE's, sorted at
* boot for resource allocation purposes
*/
- struct list_head pe_list;
+ struct list_head pe_dma_list;
} ioda;
};