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authorAlexander Sverdlin <alexander.sverdlin.ext@nsn.com>2013-04-11 17:29:39 +0200
committerRalf Baechle <ralf@linux-mips.org>2013-05-08 01:19:07 +0200
commitd41d547a419ca2d4df867a40a553abfe0c3df1d6 (patch)
tree219b32ac02ac3d0d03d7dcade765d512821a89a8 /arch/mips/kernel/Makefile
parentf560fabdf3f3fe12bd48146a6ccdf03ddf9ab12c (diff)
downloadvexpress-lsk-d41d547a419ca2d4df867a40a553abfe0c3df1d6.tar.gz
MIPS: octeon: Fix GPIO number in IRQ chip private data
Current GPIO chip implementation in octeon-irq is still broken, even after upstream commit 87161ccdc61862c8b49e75c21209d7f79dc758e9 (MIPS: Octeon: Fix broken interrupt controller code). It works for GPIO IRQs that have reset-default configuration, but not for edge-triggered ones. The problem is in octeon_irq_gpio_map_common(), which passes modified "hw" variable (which has range of possible values 16..31) as "gpio_line" parameter to octeon_irq_set_ciu_mapping(), which saves it in private data of the IRQ chip. Later, neither octeon_irq_gpio_setup() is able to re-configure GPIOs (cvmx_write_csr() is writing to non-existent CVMX_GPIO_BIT_CFGX), nor octeon_irq_ciu_gpio_ack() is able to acknowledge such IRQ, because "mask" is incorrect. Fix is trivial and has been tested on Cavium Octeon II -based board, including both level-triggered and edge-triggered GPIO IRQs. Signed-off-by: Alexander Sverdlin <alexander.sverdlin.ext@nsn.com> Cc: David Daney <david.daney@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4980/ Acked-by: John Crispin <blogic@openwrt.org>
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