path: root/arch/c6x/kernel
diff options
authorMark Salter <msalter@redhat.com>2011-10-04 12:12:20 -0400
committerMark Salter <msalter@redhat.com>2011-10-06 19:47:33 -0400
commit041cadca7008f08fb4785f2288c8127c16faa529 (patch)
tree19008ae2e32faf489f85e00838a571a5295c79f4 /arch/c6x/kernel
parentc1a144d77a6ca3a14ba3c0fec30bc4fd20b3d817 (diff)
C6X: devicetree support
This is the basic devicetree support for C6X. Currently, four boards are supported. Each one uses a different SoC part. Two of the four supported SoCs are multicore. One with 3 cores and the other with 6 cores. There is no coherency between the core-level caches, so SMP is not an option. It is possible to run separate kernel instances on the various cores. There is currently no C6X bootloader support for device trees so we build in the DTB for now. There are some interesting twists to the hardware which are of note for device tree support. Each core has its own interrupt controller which is controlled by special purpose core registers. This core controller provides 12 general purpose prioritized interrupt sources. Each core is contained within a hardware "module" which provides L1 and L2 caches, power control, and another interrupt controller which cascades into the core interrupt controller. These core module functions are controlled by memory mapped registers. The addresses for these registers are the same for each core. That is, when coreN accesses a module-level MMIO register at a given address, it accesses the register for coreN even though other cores would use the same address to access the register in the module containing those cores. Other hardware modules (timers, enet, etc) which are memory mapped can be accessed by all cores. The timers need some further explanation for multicore SoCs. Even though all timer control registers are visible to all cores, interrupt routing or other considerations may make a given timer more suitable for use by a core than some other timer. Because of this and the desire to have the same image run on more than one core, the timer nodes have a "ti,core-mask" property which is used by the driver to scan for a suitable timer to use. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/c6x/kernel')
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/c6x/kernel/devicetree.c b/arch/c6x/kernel/devicetree.c
new file mode 100644
index 00000000000..bdb56f09d0a
--- /dev/null
+++ b/arch/c6x/kernel/devicetree.c
@@ -0,0 +1,53 @@
+ * Architecture specific OF callbacks.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ * Author: Mark Salter <msalter@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/initrd.h>
+#include <linux/memblock.h>
+void __init early_init_devtree(void *params)
+ /* Setup flat device-tree pointer */
+ initial_boot_params = params;
+ /* Retrieve various informations from the /chosen node of the
+ * device-tree, including the platform type, initrd location and
+ * size and more ...
+ */
+ of_scan_flat_dt(early_init_dt_scan_chosen, c6x_command_line);
+ /* Scan memory nodes and rebuild MEMBLOCKs */
+ of_scan_flat_dt(early_init_dt_scan_root, NULL);
+ of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+void __init early_init_dt_setup_initrd_arch(unsigned long start,
+ unsigned long end)
+ initrd_start = (unsigned long)__va(start);
+ initrd_end = (unsigned long)__va(end);
+ initrd_below_start_ok = 1;
+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
+ c6x_add_memory(base, size);
+void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
+ return __va(memblock_alloc(size, align));