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authorDavid Woodhouse <David.Woodhouse@intel.com>2012-10-09 15:03:21 +0100
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-10-09 15:04:25 +0100
commitffe315012510165ce82e4dd4767f0a5dba9edbf7 (patch)
treef601cd980af9d0ced5ca9aedecef4fa0d2ca0e15 /arch/arm/boot/dts
parente2d3a35ee427aaba99b6c68a56609ce276c51270 (diff)
parent4a8e43feeac7996b8de2d5b2823e316917493df4 (diff)
downloadvexpress-lsk-ffe315012510165ce82e4dd4767f0a5dba9edbf7.tar.gz
Merge tag 'disintegrate-mtd-20121009' of git://git.infradead.org/users/dhowells/linux-headers
UAPI Disintegration 2012-10-09 Conflicts: MAINTAINERS arch/arm/configs/bcmring_defconfig arch/arm/mach-imx/clk-imx51-imx53.c drivers/mtd/nand/Kconfig drivers/mtd/nand/bcm_umi_nand.c drivers/mtd/nand/nand_bcm_umi.h drivers/mtd/nand/orion_nand.c
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile108
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts60
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts100
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi76
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi5
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi44
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts4
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi57
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi70
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi70
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi3
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi5
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi5
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi4
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b.dts12
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi39
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi (renamed from arch/arm/boot/dts/db8500.dtsi)71
-rw-r--r--arch/arm/boot/dts/dove-cm-a510.dts38
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts42
-rw-r--r--arch/arm/boot/dts/dove-dove-db.dts38
-rw-r--r--arch/arm/boot/dts/dove.dtsi143
-rw-r--r--arch/arm/boot/dts/ea3250.dts109
-rw-r--r--arch/arm/boot/dts/elpida_ecb240abacn.dtsi67
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi248
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts77
-rw-r--r--arch/arm/boot/dts/exynos4210-pinctrl.dtsi457
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts54
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts237
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi201
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts59
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi60
-rw-r--r--arch/arm/boot/dts/highbank.dts18
-rw-r--r--arch/arm/boot/dts/hrefv60plus.dts95
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts3
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts57
-rw-r--r--arch/arm/boot/dts/imx23-stmp378x_devb.dts2
-rw-r--r--arch/arm/boot/dts/imx23.dtsi43
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts6
-rw-r--r--arch/arm/boot/dts/imx27.dtsi1
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts2
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts99
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts29
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts83
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts23
-rw-r--r--arch/arm/boot/dts/imx28.dtsi128
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts48
-rw-r--r--arch/arm/boot/dts/imx51.dtsi146
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts59
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts39
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts42
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts46
-rw-r--r--arch/arm/boot/dts/imx53.dtsi199
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts21
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts31
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts25
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi325
-rw-r--r--arch/arm/boot/dts/integrator.dtsi76
-rw-r--r--arch/arm/boot/dts/integratorap.dts68
-rw-r--r--arch/arm/boot/dts/integratorcp.dts110
-rw-r--r--arch/arm/boot/dts/kirkwood-dnskw.dtsi10
-rw-r--r--arch/arm/boot/dts/kirkwood-dockstar.dts57
-rw-r--r--arch/arm/boot/dts/kirkwood-iconnect.dts56
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts105
-rw-r--r--arch/arm/boot/dts/kirkwood-km_kirkwood.dts29
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi12
-rw-r--r--arch/arm/boot/dts/mmp2.dtsi5
-rw-r--r--arch/arm/boot/dts/msm8660-surf.dts19
-rw-r--r--arch/arm/boot/dts/msm8960-cdp.dts41
-rw-r--r--arch/arm/boot/dts/omap2420-h4.dts2
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi48
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi92
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts (renamed from arch/arm/boot/dts/omap3-beagle.dts)54
-rw-r--r--arch/arm/boot/dts/omap3-evm.dts13
-rw-r--r--arch/arm/boot/dts/omap3-overo.dtsi57
-rw-r--r--arch/arm/boot/dts/omap3-tobi.dts35
-rw-r--r--arch/arm/boot/dts/omap3.dtsi94
-rw-r--r--arch/arm/boot/dts/omap36xx.dtsi25
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts11
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts127
-rw-r--r--arch/arm/boot/dts/omap4.dtsi203
-rw-r--r--arch/arm/boot/dts/omap5-evm.dts64
-rw-r--r--arch/arm/boot/dts/omap5.dtsi139
-rw-r--r--arch/arm/boot/dts/phy3250.dts16
-rw-r--r--arch/arm/boot/dts/prima2-cb.dts424
-rw-r--r--arch/arm/boot/dts/prima2-evb.dts37
-rw-r--r--arch/arm/boot/dts/prima2.dtsi640
-rw-r--r--arch/arm/boot/dts/pxa27x.dtsi14
-rw-r--r--arch/arm/boot/dts/pxa2xx.dtsi132
-rw-r--r--arch/arm/boot/dts/pxa3xx.dtsi32
-rw-r--r--arch/arm/boot/dts/pxa910-dkb.dts137
-rw-r--r--arch/arm/boot/dts/pxa910.dtsi9
-rw-r--r--arch/arm/boot/dts/snowball.dts19
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts220
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts58
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts173
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts50
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts186
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi449
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts53
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts206
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts295
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts87
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts98
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dts171
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi475
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi2
-rw-r--r--arch/arm/boot/dts/tps65217.dtsi56
-rw-r--r--arch/arm/boot/dts/tps65910.dtsi86
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi6
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi29
-rw-r--r--arch/arm/boot/dts/vt8500-bv07.dts36
-rw-r--r--arch/arm/boot/dts/vt8500.dtsi116
-rw-r--r--arch/arm/boot/dts/wm8505-ref.dts36
-rw-r--r--arch/arm/boot/dts/wm8505.dtsi143
-rw-r--r--arch/arm/boot/dts/wm8650-mid.dts36
-rw-r--r--arch/arm/boot/dts/wm8650.dtsi147
-rw-r--r--arch/arm/boot/dts/xenvm-4.2.dts68
120 files changed, 9298 insertions, 1137 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
new file mode 100644
index 00000000000..29f541f0e65
--- /dev/null
+++ b/arch/arm/boot/dts/Makefile
@@ -0,0 +1,108 @@
+ifeq ($(CONFIG_OF),y)
+
+dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
+ at91sam9263ek.dtb \
+ at91sam9g20ek_2mmc.dtb \
+ at91sam9g20ek.dtb \
+ at91sam9g25ek.dtb \
+ at91sam9m10g45ek.dtb \
+ at91sam9n12ek.dtb \
+ ethernut5.dtb \
+ evk-pro3.dtb \
+ kizbox.dtb \
+ tny_a9260.dtb \
+ tny_a9263.dtb \
+ tny_a9g20.dtb \
+ usb_a9260.dtb \
+ usb_a9263.dtb \
+ usb_a9g20.dtb
+dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
+ dove-cubox.dtb \
+ dove-dove-db.dtb
+dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
+ exynos4210-smdkv310.dtb \
+ exynos4210-trats.dtb \
+ exynos5250-smdk5250.dtb
+dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
+dtb-$(CONFIG_ARCH_IMX5) += imx51-babbage.dtb \
+ imx53-ard.dtb \
+ imx53-evk.dtb \
+ imx53-qsb.dtb \
+ imx53-smd.dtb
+dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
+ imx6q-sabrelite.dtb \
+ imx6q-sabresd.dtb
+dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
+dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
+ kirkwood-dns325.dtb \
+ kirkwood-dockstar.dtb \
+ kirkwood-dreamplug.dtb \
+ kirkwood-goflexnet.dtb \
+ kirkwood-ib62x0.dtb \
+ kirkwood-iconnect.dtb \
+ kirkwood-iomega_ix2_200.dtb \
+ kirkwood-km_kirkwood.dtb \
+ kirkwood-lschlv2.dtb \
+ kirkwood-lsxhl.dtb \
+ kirkwood-ts219-6281.dtb \
+ kirkwood-ts219-6282.dtb
+dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
+ msm8960-cdp.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
+ armada-xp-db.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
+ imx53-ard.dtb \
+ imx53-evk.dtb \
+ imx53-qsb.dtb \
+ imx53-smd.dtb \
+ imx6q-arm2.dtb \
+ imx6q-sabrelite.dtb \
+ imx6q-sabresd.dtb
+dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
+ imx23-olinuxino.dtb \
+ imx23-stmp378x_devb.dtb \
+ imx28-apx4devkit.dtb \
+ imx28-cfa10036.dtb \
+ imx28-cfa10049.dtb \
+ imx28-evk.dtb \
+ imx28-m28evk.dtb \
+ imx28-tx28.dtb
+dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
+ omap3-beagle-xm.dtb \
+ omap3-evm.dtb \
+ omap3-tobi.dtb \
+ omap4-panda.dtb \
+ omap4-pandaES.dtb \
+ omap4-var_som.dtb \
+ omap4-sdp.dtb \
+ omap5-evm.dtb
+dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+dtb-$(CONFIG_ARCH_U8500) += snowball.dtb
+dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
+ r8a7740-armadillo800eva.dtb \
+ sh73a0-kzm9g.dtb
+dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
+ spear1340-evb.dtb
+dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
+ spear310-evb.dtb \
+ spear320-evb.dtb
+dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+ tegra20-medcom-wide.dtb \
+ tegra20-paz00.dtb \
+ tegra20-plutux.dtb \
+ tegra20-seaboard.dtb \
+ tegra20-tec.dtb \
+ tegra20-trimslice.dtb \
+ tegra20-ventana.dtb \
+ tegra20-whistler.dtb \
+ tegra30-cardhu-a02.dtb \
+ tegra30-cardhu-a04.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
+ vexpress-v2p-ca9.dtb \
+ vexpress-v2p-ca15-tc1.dtb \
+ vexpress-v2p-ca15_a7.dtb \
+ xenvm-4.2.dtb
+
+endif
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a9af4db7234..c634f87e230 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -17,4 +17,64 @@
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
+
+ ocp {
+ uart1: serial@44e09000 {
+ status = "okay";
+ };
+
+ i2c1: i2c@44e0b000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@24 {
+ reg = <0x24>;
+ };
+
+ };
+ };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+ regulators {
+ dcdc1_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1325000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@3 {
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@6 {
+ regulator-always-on;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d6a97d9eff7..185d6325a45 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -17,4 +17,104 @@
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
+
+ ocp {
+ uart1: serial@44e09000 {
+ status = "okay";
+ };
+
+ i2c1: i2c@44e0b000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@2d {
+ reg = <0x2d>;
+ };
+ };
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+};
+
+/include/ "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1312500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-always-on;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 59509c48d7e..bb31bff0199 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -69,90 +69,146 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
+ reg = <0x44e07000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <96>;
};
- gpio2: gpio@4804C000 {
+ gpio2: gpio@4804c000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
+ reg = <0x4804c000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <98>;
};
- gpio3: gpio@481AC000 {
+ gpio3: gpio@481ac000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
+ reg = <0x481ac000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <32>;
};
- gpio4: gpio@481AE000 {
+ gpio4: gpio@481ae000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
+ reg = <0x481ae000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <62>;
};
- uart1: serial@44E09000 {
+ uart1: serial@44e09000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
+ reg = <0x44e09000 0x2000>;
+ interrupt-parent = <&intc>;
+ interrupts = <72>;
+ status = "disabled";
};
uart2: serial@48022000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
+ reg = <0x48022000 0x2000>;
+ interrupt-parent = <&intc>;
+ interrupts = <73>;
+ status = "disabled";
};
uart3: serial@48024000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
+ reg = <0x48024000 0x2000>;
+ interrupt-parent = <&intc>;
+ interrupts = <74>;
+ status = "disabled";
};
- uart4: serial@481A6000 {
+ uart4: serial@481a6000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
+ reg = <0x481a6000 0x2000>;
+ interrupt-parent = <&intc>;
+ interrupts = <44>;
+ status = "disabled";
};
- uart5: serial@481A8000 {
+ uart5: serial@481a8000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart5";
clock-frequency = <48000000>;
+ reg = <0x481a8000 0x2000>;
+ interrupt-parent = <&intc>;
+ interrupts = <45>;
+ status = "disabled";
};
- uart6: serial@481AA000 {
+ uart6: serial@481aa000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart6";
clock-frequency = <48000000>;
+ reg = <0x481aa000 0x2000>;
+ interrupt-parent = <&intc>;
+ interrupts = <46>;
+ status = "disabled";
};
- i2c1: i2c@44E0B000 {
+ i2c1: i2c@44e0b000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
+ reg = <0x44e0b000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <70>;
+ status = "disabled";
};
- i2c2: i2c@4802A000 {
+ i2c2: i2c@4802a000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
+ reg = <0x4802a000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <71>;
+ status = "disabled";
};
- i2c3: i2c@4819C000 {
+ i2c3: i2c@4819c000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
+ reg = <0x4819c000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <30>;
+ status = "disabled";
+ };
+
+ wdt2: wdt@44e35000 {
+ compatible = "ti,omap3-wdt";
+ ti,hwmods = "wd_timer2";
+ reg = <0x44e35000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <91>;
};
};
};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932a5a7..16cc82cdaa8 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,11 @@
reg = <0xd0020300 0x30>;
interrupts = <37>, <38>, <39>, <40>;
};
+
+ addr-decoding@d0020000 {
+ compatible = "marvell,armada-addr-decoding-controller";
+ reg = <0xd0020000 0x258>;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc8333..2069151afe0 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -21,6 +21,12 @@
model = "Marvell Armada 370 family SoC";
compatible = "marvell,armada370", "marvell,armada-370-xp";
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ };
+
mpic: interrupt-controller@d0020000 {
reg = <0xd0020a00 0x1d0>,
<0xd0021870 0x58>;
@@ -31,5 +37,43 @@
compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x100>;
};
+
+ pinctrl {
+ compatible = "marvell,mv88f6710-pinctrl";
+ reg = <0xd0018000 0x38>;
+ };
+
+ gpio0: gpio@d0018100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0xd0018100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <82>, <83>, <84>, <85>;
+ };
+
+ gpio1: gpio@d0018140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0xd0018140 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <87>, <88>, <89>, <90>;
+ };
+
+ gpio2: gpio@d0018180 {
+ compatible = "marvell,orion-gpio";
+ reg = <0xd0018180 0x40>;
+ ngpios = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <91>;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f97040d4258..b1fc728515e 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,11 +14,11 @@
*/
/dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Evaluation Board";
- compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+ compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
new file mode 100644
index 00000000000..ea355192be6
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+ model = "Marvell Armada XP MV78230 SoC";
+ compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ };
+
+ soc {
+ pinctrl {
+ compatible = "marvell,mv78230-pinctrl";
+ reg = <0xd0018000 0x38>;
+ };
+
+ gpio0: gpio@d0018100 {
+ compatible = "marvell,armadaxp-gpio";
+ reg = <0xd0018100 0x40>,
+ <0xd0018800 0x30>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <16>, <17>, <18>, <19>;
+ };
+
+ gpio1: gpio@d0018140 {
+ compatible = "marvell,armadaxp-gpio";
+ reg = <0xd0018140 0x40>,
+ <0xd0018840 0x30>;
+ ngpios = <17>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <20>, <21>, <22>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
new file mode 100644
index 00000000000..2057863f3df
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+ model = "Marvell Armada XP MV78260 SoC";
+ compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ };
+
+ soc {
+ pinctrl {
+ compatible = "marvell,mv78260-pinctrl";
+ reg = <0xd0018000 0x38>;
+ };
+
+ gpio0: gpio@d0018100 {
+ compatible = "marvell,armadaxp-gpio";
+ reg = <0xd0018100 0x40>,
+ <0xd0018800 0x30>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <16>, <17>, <18>, <19>;
+ };
+
+ gpio1: gpio@d0018140 {
+ compatible = "marvell,armadaxp-gpio";
+ reg = <0xd0018140 0x40>,
+ <0xd0018840 0x30>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <20>, <21>, <22>, <23>;
+ };
+
+ gpio2: gpio@d0018180 {
+ compatible = "marvell,armadaxp-gpio";
+ reg = <0xd0018180 0x40>,
+ <0xd0018870 0x30>;
+ ngpios = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <24>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
new file mode 100644
index 00000000000..ffac9837379
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+ model = "Marvell Armada XP MV78460 SoC";
+ compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ };
+
+ soc {
+ pinctrl {
+ compatible = "marvell,mv78460-pinctrl";
+ reg = <0xd0018000 0x38>;
+ };
+
+ gpio0: gpio@d0018100 {
+ compatible = "marvell,armadaxp-gpio";
+ reg = <0xd0018100 0x40>,
+ <0xd0018800 0x30>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <16>, <17>, <18>, <19>;
+ };
+
+ gpio1: gpio@d0018140 {
+ compatible = "marvell,armadaxp-gpio";
+ reg = <0xd0018140 0x40>,
+ <0xd0018840 0x30>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <20>, <21>, <22>, <23>;
+ };
+
+ gpio2: gpio@d0018180 {
+ compatible = "marvell,armadaxp-gpio";
+ reg = <0xd0018180 0x40>,
+ <0xd0018870 0x30>;
+ ngpios = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <24>;
+ };
+ };
+ };
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 66389c1c6f6..7c95f76398d 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -104,6 +104,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioB: gpio@fffff600 {
@@ -113,6 +114,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioC: gpio@fffff800 {
@@ -122,6 +124,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index b460d6ce9eb..195019b7ca0 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -95,6 +95,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioB: gpio@fffff400 {
@@ -104,6 +105,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioC: gpio@fffff600 {
@@ -113,6 +115,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioD: gpio@fffff800 {
@@ -122,6 +125,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioE: gpio@fffffa00 {
@@ -131,6 +135,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
dbgu: serial@ffffee00 {
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 7829a4d0cb2..96514c134e5 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -15,7 +15,7 @@
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
- bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+ bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
};
ahb {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bafa8806fc1..63751b1e744 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -113,6 +113,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioB: gpio@fffff400 {
@@ -122,6 +123,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioC: gpio@fffff600 {
@@ -131,6 +133,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioD: gpio@fffff800 {
@@ -140,6 +143,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioE: gpio@fffffa00 {
@@ -149,6 +153,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
dbgu: serial@ffffee00 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index bfac0dfc332..ef9336ae961 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -107,6 +107,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioB: gpio@fffff600 {
@@ -116,6 +117,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioC: gpio@fffff800 {
@@ -125,6 +127,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioD: gpio@fffffa00 {
@@ -134,6 +137,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 4a18c393b13..8a387a8d61b 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -115,6 +115,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioB: gpio@fffff600 {
@@ -124,6 +125,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioC: gpio@fffff800 {
@@ -133,6 +135,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
pioD: gpio@fffffa00 {
@@ -142,6 +145,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
};
dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
new file mode 100644
index 00000000000..7dd860f83f9
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/memreserve/ 0x0c000000 0x04000000;
+/include/ "bcm2835.dtsi"
+
+/ {
+ compatible = "raspberrypi,model-b", "brcm,bcm2835";
+ model = "Raspberry Pi Model B";
+
+ memory {
+ reg = <0 0x10000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
new file mode 100644
index 00000000000..0b619398532
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -0,0 +1,39 @@
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm2835";
+ model = "BCM2835";
+ interrupt-parent = <&intc>;
+
+ chosen {
+ bootargs = "earlyprintk console=ttyAMA0";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x7e000000 0x20000000 0x02000000>;
+
+ timer {
+ compatible = "brcm,bcm2835-system-timer";
+ reg = <0x7e003000 0x1000>;
+ interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
+ clock-frequency = <1000000>;
+ };
+
+ intc: interrupt-controller {
+ compatible = "brcm,bcm2835-armctrl-ic";
+ reg = <0x7e00b200 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart@20201000 {
+ compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+ reg = <0x7e201000 0x1000>;
+ interrupts = <2 25>;
+ clock-frequency = <3000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 3180a9c588b..748ba7aa746 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -194,6 +194,8 @@
interrupts = <0 47 0x4>;
#address-cells = <1>;
#size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
ranges;
prcmu-timer-4@80157450 {
@@ -330,6 +332,7 @@
ab8500@5 {
compatible = "stericsson,ab8500";
reg = <5>; /* mailbox 5 is i2c */
+ interrupt-parent = <&intc>;
interrupts = <0 40 0x4>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -371,7 +374,7 @@
};
ab8500-ponkey {
- compatible = "stericsson,ab8500-ponkey";
+ compatible = "stericsson,ab8500-poweron-key";
interrupts = <6 0x4
7 0x4>;
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
@@ -389,6 +392,12 @@
compatible = "stericsson,ab8500-debug";
};
+ codec: ab8500-codec {
+ compatible = "stericsson,ab8500-codec";
+
+ stericsson,earpeice-cmv = <950>; /* Units in mV. */
+ };
+
ab8500-regulators {
compatible = "stericsson,ab8500-regulator";
@@ -471,48 +480,63 @@
};
i2c@80004000 {
- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80004000 0x1000>;
interrupts = <0 21 0x4>;
#address-cells = <1>;
#size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
};
i2c@80122000 {
- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80122000 0x1000>;
interrupts = <0 22 0x4>;
#address-cells = <1>;
#size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
};
i2c@80128000 {
- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80128000 0x1000>;
interrupts = <0 55 0x4>;
#address-cells = <1>;
#size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
};
i2c@80110000 {
- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80110000 0x1000>;
interrupts = <0 12 0x4>;
#address-cells = <1>;
#size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
};
i2c@8012a000 {
- compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x8012a000 0x1000>;
interrupts = <0 51 0x4>;
#address-cells = <1>;
#size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
};
ssp@80002000 {
compatible = "arm,pl022", "arm,primecell";
- reg = <80002000 0x1000>;
+ reg = <0x80002000 0x1000>;
interrupts = <0 14 0x4>;
#address-cells = <1>;
#size-cells = <0>;
@@ -580,6 +604,39 @@
status = "disabled";
};
+ msp0: msp@80123000 {
+ compatible = "stericsson,ux500-msp-i2s";
+ reg = <0x80123000 0x1000>;
+ interrupts = <0 31 0x4>;
+ v-ape-supply = <&db8500_vape_reg>;
+ status = "disabled";
+ };
+
+ msp1: msp@80124000 {
+ compatible = "stericsson,ux500-msp-i2s";
+ reg = <0x80124000 0x1000>;
+ interrupts = <0 62 0x4>;
+ v-ape-supply = <&db8500_vape_reg>;
+ status = "disabled";
+ };
+
+ // HDMI sound
+ msp2: msp@80117000 {
+ compatible = "stericsson,ux500-msp-i2s";
+ reg = <0x80117000 0x1000>;
+ interrupts = <0 98 0x4>;
+ v-ape-supply = <&db8500_vape_reg>;
+ status = "disabled";
+ };
+
+ msp3: msp@80125000 {
+ compatible = "stericsson,ux500-msp-i2s";
+ reg = <0x80125000 0x1000>;
+ interrupts = <0 62 0x4>;
+ v-ape-supply = <&db8500_vape_reg>;
+ status = "disabled";
+ };
+
external-bus@50000000 {
compatible = "simple-bus";
reg = <0x50000000 0x4000000>;
diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
new file mode 100644
index 00000000000..61a8062e56d
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+ model = "Compulab CM-A510";
+ compatible = "compulab,cm-a510", "marvell,dove";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+ status = "okay";
+
+ /* spi0.0: 4M Flash Winbond W25Q32BV */
+ spi-flash@0 {
+ compatible = "st,w25q32";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
new file mode 100644
index 00000000000..0adbd5a3809
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+ model = "SolidRun CuBox";
+ compatible = "solidrun,cubox", "marvell,dove";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ power {
+ label = "Power";
+ gpios = <&gpio0 18 1>;
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&uart0 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+
+&spi0 {
+ status = "okay";
+
+ /* spi0.0: 4M Flash Winbond W25Q32BV */
+ spi-flash@0 {
+ compatible = "st,w25q32";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
new file mode 100644
index 00000000000..e5a920beab4
--- /dev/null
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+ model = "Marvell DB-MV88AP510-BP Development Board";
+ compatible = "marvell,dove-db", "marvell,dove";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+ status = "okay";
+
+ /* spi0.0: 4M Flash ST-M25P32-VMF6P */
+ spi-flash@0 {
+ compatible = "st,m25p32";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
new file mode 100644
index 00000000000..96fb824b5e6
--- /dev/null
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -0,0 +1,143 @@
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "marvell,dove";
+ model = "Marvell Armada 88AP510 SoC";
+
+ interrupt-parent = <&intc>;
+
+ intc: interrupt-controller {
+ compatible = "marvell,orion-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xf1020204 0x04>,
+ <0xf1020214 0x04>;
+ };
+
+ mbus@f1000000 {
+ compatible = "simple-bus";
+ ranges = <0 0xf1000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@12000 {
+ compatible = "ns16550a";
+ reg = <0x12000 0x100>;
+ reg-shift = <2>;
+ interrupts = <7>;
+ clock-frequency = <166666667>;
+ status = "disabled";
+ };
+
+ uart1: serial@12100 {
+ compatible = "ns16550a";
+ reg = <0x12100 0x100>;
+ reg-shift = <2>;
+ interrupts = <8>;
+ clock-frequency = <166666667>;
+ status = "disabled";
+ };
+
+ uart2: serial@12200 {
+ compatible = "ns16550a";
+ reg = <0x12000 0x100>;
+ reg-shift = <2>;
+ interrupts = <9>;
+ clock-frequency = <166666667>;
+ status = "disabled";
+ };
+
+ uart3: serial@12300 {
+ compatible = "ns16550a";
+ reg = <0x12100 0x100>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clock-frequency = <166666667>;
+ status = "disabled";
+ };
+
+ wdt: wdt@20300 {
+ compatible = "marvell,orion-wdt";
+ reg = <0x20300 0x28>;
+ };
+
+ gpio0: gpio@d0400 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0xd0400 0x20>;
+ ngpio = <32>;
+ interrupts = <12>, <13>, <14>, <60>;
+ };
+
+ gpio1: gpio@d0420 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0xd0420 0x20>;
+ ngpio = <32>;
+ interrupts = <61>;
+ };
+
+ gpio2: gpio@e8400 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0xe8400 0x0c>;
+ ngpio = <8>;
+ };
+
+ spi0: spi@10600 {
+ compatible = "marvell,orion-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <6>;
+ reg = <0x10600 0x28>;
+ status = "disabled";
+ };
+
+ spi1: spi@14600 {
+ compatible = "marvell,orion-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ interrupts = <5>;
+ reg = <0x14600 0x28>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@11000 {
+ compatible = "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <11>;
+ clock-frequency = <400000>;
+ timeout-ms = <1000>;
+ status = "disabled";
+ };
+
+ sdio0: sdio@92000 {
+ compatible = "marvell,dove-sdhci";
+ reg = <0x92000 0x100>;
+ interrupts = <35>, <37>;
+ status = "disabled";
+ };
+
+ sdio1: sdio@90000 {
+ compatible = "marvell,dove-sdhci";
+ reg = <0x90000 0x100>;
+ interrupts = <36>, <38>;
+ status = "disabled";
+ };
+
+ sata0: sata@a0000 {
+ compatible = "marvell,orion-sata";
+ reg = <0xa0000 0x2400>;
+ interrupts = <62>;
+ nr-ports = <1>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
index d79b28d9c96..a4ba31b23c8 100644
--- a/arch/arm/boot/dts/ea3250.dts
+++ b/arch/arm/boot/dts/ea3250.dts
@@ -166,9 +166,116 @@
#size-cells = <0>;
autorepeat;
button@21 {
- label = "GPIO Key UP";
+ label = "Interrupt Key";
linux,code = <103>;
gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
};
+ key1 {
+ label = "KEY1";
+ linux,code = <1>;
+ gpios = <&pca9532 0 0>;
+ };
+ key2 {
+ label = "KEY2";
+ linux,code = <2>;
+ gpios = <&pca9532 1 0>;
+ };
+ key3 {
+ label = "KEY3";
+ linux,code = <3>;
+ gpios = <&pca9532 2 0>;
+ };
+ key4 {
+ label = "KEY4";
+ linux,code = <4>;
+ gpios = <&pca9532 3 0>;
+ };
+ joy0 {
+ label = "Joystick Key 0";
+ linux,code = <10>;
+ gpios = <&gpio 2 0 0>; /* P2.0 */
+ };
+ joy1 {
+ label = "Joystick Key 1";
+ linux,code = <11>;
+ gpios = <&gpio 2 1 0>; /* P2.1 */
+ };
+ joy2 {
+ label = "Joystick Key 2";
+ linux,code = <12>;
+ gpios = <&gpio 2 2 0>; /* P2.2 */
+ };
+ joy3 {
+ label = "Joystick Key 3";
+ linux,code = <13>;
+ gpios = <&gpio 2 3 0>; /* P2.3 */
+ };
+ joy4 {
+ label = "Joystick Key 4";
+ linux,code = <14>;
+ gpios = <&gpio 2 4 0>; /* P2.4 */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* LEDs on OEM Board */
+
+ led1 {
+ gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
+ linux,default-trigger = "timer";
+ default-state = "off";
+ };
+
+ led2 {
+ gpios = <&gpio 2 10 1>; /* P2.10, active low */
+ default-state = "off";
+ };
+
+ led3 {
+ gpios = <&gpio 2 11 1>; /* P2.11, active low */
+ default-state = "off";
+ };
+
+ led4 {
+ gpios = <&gpio 2 12 1>; /* P2.12, active low */
+ default-state = "off";
+ };
+
+ /* LEDs on Base Board */
+
+ lede1 {
+ gpios = <&pca9532 8 0>;
+ default-state = "off";
+ };
+ lede2 {
+ gpios = <&pca9532 9 0>;
+ default-state = "off";
+ };
+ lede3 {
+ gpios = <&pca9532 10 0>;
+ default-state = "off";
+ };
+ lede4 {
+ gpios = <&pca9532 11 0>;
+ default-state = "off";
+ };
+ lede5 {
+ gpios = <&pca9532 12 0>;
+ default-state = "off";
+ };
+ lede6 {
+ gpios = <&pca9532 13 0>;
+ default-state = "off";
+ };
+ lede7 {
+ gpios = <&pca9532 14 0>;
+ default-state = "off";
+ };
+ lede8 {
+ gpios = <&pca9532 15 0>;
+ default-state = "off";
+ };
};
};
diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
new file mode 100644
index 00000000000..f97f70f8337
--- /dev/null
+++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Common devices used in different OMAP boards
+ */
+
+/ {
+ elpida_ECB240ABACN: lpddr2 {
+ compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+ density = <2048>;
+ io-width = <32>;
+
+ tRPab-min-tck = <3>;
+ tRCD-min-tck = <3>;
+ tWR-min-tck = <3>;
+ tRASmin-min-tck = <3>;
+ tRRD-min-tck = <2>;
+ tWTR-min-tck = <2>;
+ tXP-min-tck = <2>;
+ tRTP-min-tck = <2>;
+ tCKE-min-tck = <3>;
+ tCKESR-min-tck = <3>;
+ tFAW-min-tck = <8>;
+
+ timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <7500>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ tDQSCK-max-derated = <6000>;
+ };
+
+ timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <200000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <10000>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ tDQSCK-max-derated = <6000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
new file mode 100644
index 00000000000..a26c3dd5826
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -0,0 +1,248 @@
+/*
+ * Samsung's Exynos4 SoC series common device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ * www.linaro.org
+ *
+ * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
+ * SoCs from Exynos4 series can include this file and provide values for SoCs
+ * specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ aliases {
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ };
+
+ gic:interrupt-controller@10490000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+ };
+
+ combiner:interrupt-controller@10440000 {
+ compatible = "samsung,exynos4210-combiner";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x10440000 0x1000>;
+ };
+
+ watchdog@10060000 {
+ compatible = "samsung,s3c2410-wdt";
+ reg = <0x10060000 0x100>;
+ interrupts = <0 43 0>;
+ status = "disabled";
+ };
+
+ rtc@10070000 {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x10070000 0x100>;
+ interrupts = <0 44 0>, <0 45 0>;
+ status = "disabled";
+ };
+
+ keypad@100A0000 {
+ compatible = "samsung,s5pv210-keypad";
+ reg = <0x100A0000 0x100>;
+ interrupts = <0 109 0>;
+ status = "disabled";
+ };
+
+ sdhci@12510000 {
+ compatible = "samsung,exynos4210-sdhci";
+ reg = <0x12510000 0x100>;
+ interrupts = <0 73 0>;
+ status = "disabled";
+ };
+
+ sdhci@12520000 {
+ compatible = "samsung,exynos4210-sdhci";
+ reg = <0x12520000 0x100>;
+ interrupts = <0 74 0>;
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ compatible = "samsung,exynos4210-sdhci";
+ reg = <0x12530000 0x100>;
+ interrupts = <0 75 0>;
+ status = "disabled";
+ };
+
+ sdhci@12540000 {
+ compatible = "samsung,exynos4210-sdhci";
+ reg = <0x12540000 0x100>;
+ interrupts = <0 76 0>;
+ status = "disabled";
+ };
+
+ serial@13800000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13800000 0x100>;
+ interrupts = <0 52 0>;
+ status = "disabled";
+ };
+
+ serial@13810000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13810000 0x100>;
+ interrupts = <0 53 0>;
+ status = "disabled";
+ };
+
+ serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 54 0>;
+ status = "disabled";
+ };
+
+ serial@13830000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13830000 0x100>;
+ interrupts = <0 55 0>;
+ status = "disabled";
+ };
+
+ i2c@13860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13860000 0x100>;
+ interrupts = <0 58 0>;
+ status = "disabled";
+ };
+
+ i2c@13870000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13870000 0x100>;
+ interrupts = <0 59 0>;
+ status = "disabled";
+ };
+
+ i2c@13880000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13880000 0x100>;
+ interrupts = <0 60 0>;
+ status = "disabled";
+ };
+
+ i2c@13890000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13890000 0x100>;
+ interrupts = <0 61 0>;
+ status = "disabled";
+ };
+
+ i2c@138A0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138A0000 0x100>;
+ interrupts = <0 62 0>;
+ status = "disabled";
+ };
+
+ i2c@138B0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138B0000 0x100>;
+ interrupts = <0 63 0>;
+ status = "disabled";
+ };
+
+ i2c@138C0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138C0000 0x100>;
+ interrupts = <0 64 0>;
+ status = "disabled";
+ };
+
+ i2c@138D0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138D0000 0x100>;
+ interrupts = <0 65 0>;
+ status = "disabled";
+ };
+
+ spi_0: spi@13920000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13920000 0x100>;
+ interrupts = <0 66 0>;
+ tx-dma-channel = <&pdma0 7>; /* preliminary */
+ rx-dma-channel = <&pdma0 6>; /* preliminary */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi_1: spi@13930000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13930000 0x100>;
+ interrupts = <0 67 0>;
+ tx-dma-channel = <&pdma1 7>; /* preliminary */
+ rx-dma-channel = <&pdma1 6>; /* preliminary */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi_2: spi@13940000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13940000 0x100>;
+ interrupts = <0 68 0>;
+ tx-dma-channel = <&pdma0 9>; /* preliminary */
+ rx-dma-channel = <&pdma0 8>; /* preliminary */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "arm,amba-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma0: pdma@12680000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12680000 0x1000>;
+ interrupts = <0 35 0>;
+ };
+
+ pdma1: pdma@12690000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12690000 0x1000>;
+ interrupts = <0 36 0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 0c49caa0997..3e68f52e845 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -40,6 +40,7 @@
<&gpk2 4 2 3 3>,
<&gpk2 5 2 3 3>,
<&gpk2 6 2 3 3>;
+ status = "okay";
};
sdhci@12510000 {
@@ -53,6 +54,7 @@
<&gpk0 4 2 3 3>,
<&gpk0 5 2 3 3>,
<&gpk0 6 2 3 3>;
+ status = "okay";
};
gpio_keys {
@@ -62,88 +64,45 @@
up {
label = "Up";
- gpios = <&gpx2 0 0 0 2>;
+ gpios = <&gpx2 0 0 0x10000 2>;
linux,code = <103>;
+ gpio-key,wakeup;
};
down {
label = "Down";
- gpios = <&gpx2 1 0 0 2>;
+ gpios = <&gpx2 1 0 0x10000 2>;
linux,code = <108>;
+ gpio-key,wakeup;
};
back {
label = "Back";
- gpios = <&gpx1 7 0 0 2>;
+ gpios = <&gpx1 7 0 0x10000 2>;
linux,code = <158>;
+ gpio-key,wakeup;
};
home {
label = "Home";
- gpios = <&gpx1 6 0 0 2>;
+ gpios = <&gpx1 6 0 0x10000 2>;
linux,code = <102>;
+ gpio-key,wakeup;
};
menu {
label = "Menu";
- gpios = <&gpx1 5 0 0 2>;
+ gpios = <&gpx1 5 0 0x10000 2>;
linux,code = <139>;
+ gpio-key,wakeup;
};
};
- keypad@100A0000 {
- status = "disabled";
- };
-
- sdhci@12520000 {
- status = "disabled";
- };
-
- sdhci@12540000 {
- status = "disabled";
- };
-
- i2c@13860000 {
- status = "disabled";
- };
-
- i2c@13870000 {
- status = "disabled";
- };
-
- i2c@13880000 {
- status = "disabled";
- };
-
- i2c@13890000 {
- status = "disabled";
- };
-
- i2c@138A0000 {
- status = "disabled";
- };
-
- i2c@138B0000 {
- status = "disabled";
- };
-
- i2c@138C0000 {
- status = "disabled";
- };
-
- i2c@138D0000 {
- status = "disabled";
- };
-
- spi_0: spi@13920000 {
- status = "disabled";
- };
-
- spi_1: spi@13930000 {
- status = "disabled";
- };
-
- spi_2: spi@13940000 {
- status = "disabled";
+ leds {
+ compatible = "gpio-leds";
+ status {
+ gpios = <&gpx1 3 0 0x10000 2>;
+ linux,default-trigger = "heartbeat";
+ };
};
};
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 00000000000..b12cf272ad0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ * www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@11400000 {
+ uart0_data: uart0-data {
+ samsung,pins = "gpa0-0", "gpa0-1";
+ samsung,pin-function = <0x2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = "gpa0-2", "gpa0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = "gpa0-4", "gpa0-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c2_bus: i2c2-bus {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart_audio_a: uart-audio-a {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c3_bus: i2c3-bus {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart3_data: uart3-data {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart_audio_b: uart-audio-b {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c4_bus: i2c4-bus {
+ samsung,pins = "gpb-2", "gpb-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c5_bus: i2c5-bus {
+ samsung,pins = "gpb-6", "gpb-7";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2s1_bus: i2s1-bus {
+ samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+ "gpc0-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm1_bus: pcm1-bus {
+ samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+ "gpc0-4";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ ac97_bus: ac97-bus {
+ samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+ "gpc0-4";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2s2_bus: i2s2-bus {
+ samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+ "gpc1-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm2_bus: pcm2-bus {
+ samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+ "gpc1-4";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ spdif_bus: spdif-bus {
+ samsung,pins = "gpc1-0", "gpc1-1";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c6_bus: i2c6-bus {
+ samsung,pins = "gpc1-3", "gpc1-4";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
+ samsung,pin-function = <5>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c7_bus: i2c7-bus {
+ samsung,pins = "gpd0-2", "gpd0-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c0_bus: i2c0-bus {
+ samsung,pins = "gpd1-0", "gpd1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c1_bus: i2c1-bus {
+ samsung,pins = "gpd1-2", "gpd1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
+ pinctrl@11000000 {
+ sd0_clk: sd0-clk {
+ samsung,pins = "gpk0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd0_cmd: sd0-cmd {
+ samsung,pins = "gpk0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd0_cd: sd0-cd {
+ samsung,pins = "gpk0-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd0_bus1: sd0-bus-width1 {
+ samsung,pins = "gpk0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd0_bus8: sd0-bus-width8 {
+ samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd4_clk: sd4-clk {
+ samsung,pins = "gpk0-0";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd4_cmd: sd4-cmd {
+ samsung,pins = "gpk0-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd4_cd: sd4-cd {
+ samsung,pins = "gpk0-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd4_bus1: sd4-bus-width1 {
+ samsung,pins = "gpk0-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd4_bus4: sd4-bus-width4 {
+ samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd4_bus8: sd4-bus-width8 {
+ samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <4>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd1_clk: sd1-clk {
+ samsung,pins = "gpk1-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pins = "gpk1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd1_cd: sd1-cd {
+ samsung,pins = "gpk1-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pins = "gpk1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpk2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpk2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpk2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpk2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd2_bus8: sd2-bus-width8 {
+ samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd3_clk: sd3-clk {
+ samsung,pins = "gpk3-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd3_cmd: sd3-cmd {
+ samsung,pins = "gpk3-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd3_cd: sd3-cd {
+ samsung,pins = "gpk3-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd3_bus1: sd3-bus-width1 {
+ samsung,pins = "gpk3-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd3_bus4: sd3-bus-width4 {
+ samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ eint0: ext-int0 {
+ samsung,pins = "gpx0-0";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ eint8: ext-int8 {
+ samsung,pins = "gpx1-0";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ eint15: ext-int15 {
+ samsung,pins = "gpx1-7";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ eint16: ext-int16 {
+ samsung,pins = "gpx2-0";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ eint31: ext-int31 {
+ samsung,pins = "gpx3-7";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
+ pinctrl@03860000 {
+ i2s0_bus: i2s0-bus {
+ samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+ "gpz-4", "gpz-5", "gpz-6";
+ samsung,pin-function = <0x2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+ "gpz-4";
+ samsung,pin-function = <0x3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 1beccc8f14f..63610c3ba3a 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -26,7 +26,7 @@
};
chosen {
- bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
+ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
};
sdhci@12530000 {
@@ -40,6 +40,7 @@
<&gpk2 4 2 3 3>,
<&gpk2 5 2 3 3>,
<&gpk2 6 2 3 3>;
+ status = "okay";
};
keypad@100A0000 {
@@ -47,6 +48,7 @@
samsung,keypad-num-columns = <8>;
linux,keypad-no-autorepeat;
linux,keypad-wakeup;
+ status = "okay";
row-gpios = <&gpx2 0 3 3 0>,
<&gpx2 1 3 3 0>;
@@ -128,6 +130,7 @@
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpd1 0 2 3 0>,
<&gpd1 1 2 3 0>;
+ status = "okay";
eeprom@50 {
compatible = "samsung,24ad0xd1";
@@ -140,58 +143,11 @@
};
};
- sdhci@12510000 {
- status = "disabled";
- };
-
- sdhci@12520000 {
- status = "disabled";
- };
-
- sdhci@12540000 {
- status = "disabled";
- };
-
- i2c@13870000 {
- status = "disabled";
- };
-
- i2c@13880000 {
- status = "disabled";
- };
-
- i2c@13890000 {
- status = "disabled";
- };
-
- i2c@138A0000 {
- status = "disabled";
- };
-
- i2c@138B0000 {
- status = "disabled";
- };
-
- i2c@138C0000 {
- status = "disabled";
- };
-
- i2c@138D0000 {
- status = "disabled";
- };
-
- spi_0: spi@13920000 {
- status = "disabled";
- };
-
- spi_1: spi@13930000 {
- status = "disabled";
- };
-
spi_2: spi@13940000 {
gpios = <&gpc1 1 5 3 0>,
<&gpc1 3 5 3 0>,
<&gpc1 4 5 3 0>;
+ status = "okay";
w25x80@0 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
new file mode 100644
index 00000000000..73567b843e7
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -0,0 +1,237 @@
+/*
+ * Samsung's Exynos4210 based Trats board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Trats board which is based on
+ * Samsung's Exynos4210 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4210.dtsi"
+
+/ {
+ model = "Samsung Trats based on Exynos4210";
+ compatible = "samsung,trats", "samsung,exynos4210";
+
+ memory {
+ reg = <0x40000000 0x20000000
+ 0x60000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
+ };
+
+ vemmc_reg: voltage-regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpk0 2 1 0 0>;
+ enable-active-high;
+ };
+
+ sdhci_emmc: sdhci@12510000 {
+ bus-width = <8>;
+ non-removable;
+ broken-voltage;
+ gpios = <&gpk0 0 2 0 3>,
+ <&gpk0 1 2 0 3>,
+ <&gpk0 3 2 2 3>,
+ <&gpk0 4 2 2 3>,
+ <&gpk0 5 2 2 3>,
+ <&gpk0 6 2 2 3>,
+ <&gpk1 3 3 3 3>,
+ <&gpk1 4 3 3 3>,
+ <&gpk1 5 3 3 3>,
+ <&gpk1 6 3 3 3>;
+ vmmc-supply = <&vemmc_reg>;
+ status = "okay";
+ };
+
+ serial@13800000 {
+ status = "okay";
+ };
+
+ serial@13810000 {
+ status = "okay";
+ };
+
+ serial@13820000 {
+ status = "okay";
+ };
+
+ serial@13830000 {
+ status = "okay";
+ };
+
+ i2c@138B0000 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ gpios = <&gpb 6 3 3 0>,
+ <&gpb 7 3 3 0>;
+ status = "okay";
+
+ max8997_pmic@66 {
+ compatible = "maxim,max8997-pmic";
+
+ reg = <0x66>;
+
+ max8997,pmic-buck1-uses-gpio-dvs;
+ max8997,pmic-buck2-uses-gpio-dvs;
+ max8997,pmic-buck5-uses-gpio-dvs;
+
+ max8997,pmic-ignore-gpiodvs-side-effect;
+ max8997,pmic-buck125-default-dvs-idx = <0>;
+
+ max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>,
+ <&gpx0 6 1 0 0>,
+ <&gpl0 0 1 0 0>;
+
+ max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
+ <1250000>, <1200000>,
+ <1150000>, <1100000>,
+ <1000000>, <950000>;
+
+ max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>,
+ <950000>, <900000>,
+ <1100000>, <1000000>,
+ <950000>, <900000>;
+
+ max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
+ <1200000>, <1200000>,
+ <1200000>, <1200000>,
+ <1200000>, <1200000>;
+
+ regulators {
+ valive_reg: LDO2 {
+ regulator-name = "VALIVE_1.1V_C210";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ vusb_reg: LDO3 {
+ regulator-name = "VUSB_1.1V_C210";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ vmipi_reg: LDO4 {
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vpda_reg: LDO6 {
+ regulator-name = "VCC_1.8V_PDA";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcam_reg: LDO7 {
+ regulator-name = "CAM_ISP_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vusbdac_reg: LDO8 {
+ regulator-name = "VUSB/VDAC_3.3V_C210";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vccpda_reg: LDO9 {
+ regulator-name = "VCC_2.8V_PDA";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ vpll_reg: LDO10 {
+ regulator-name = "VPLL_1.1V_C210";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ vcclcd_reg: LDO13 {
+ regulator-name = "VCC_3.3V_LCD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vlcd_reg: LDO15 {
+ regulator-name = "VLCD_2.2V";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ camsensor_reg: LDO16 {
+ regulator-name = "CAM_SENSOR_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddq_reg: LDO21 {
+ regulator-name = "VDDQ_M1M2_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ varm_breg: BUCK1 {
+ regulator-name = "VARM_1.2V_C210";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ vint_breg: BUCK2 {
+ regulator-name = "VINT_1.1V_C210";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ camisp_breg: BUCK4 {
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vmem_breg: BUCK5 {
+ regulator-name = "VMEM_1.2V_C210";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vccsub_breg: BUCK7 {
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ safe1_sreg: ESAFEOUT1 {
+ regulator-name = "SAFEOUT1";
+ regulator-always-on;
+ };
+
+ safe2_sreg: ESAFEOUT2 {
+ regulator-name = "SAFEOUT2";
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe876e..214c557eda7 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,199 +19,60 @@
* published by the Free Software Foundation.
*/
-/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
+/include/ "exynos4210-pinctrl.dtsi"
/ {
compatible = "samsung,exynos4210";
- interrupt-parent = <&gic>;
aliases {
- spi0 = &spi_0;
- spi1 = &spi_1;
- spi2 = &spi_2;
+ pinctrl0 = &pinctrl_0;
+ pinctrl1 = &pinctrl_1;
+ pinctrl2 = &pinctrl_2;
};
gic:interrupt-controller@10490000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
cpu-offset = <0x8000>;
- reg = <0x10490000 0x1000>, <0x10480000 0x100>;
};
combiner:interrupt-controller@10440000 {
- compatible = "samsung,exynos4210-combiner";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
- watchdog@10060000 {
- compatible = "samsung,s3c2410-wdt";
- reg = <0x10060000 0x100>;
- interrupts = <0 43 0>;
- };
-
- rtc@10070000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x10070000 0x100>;
- interrupts = <0 44 0>, <0 45 0>;
- };
-
- keypad@100A0000 {
- compatible = "samsung,s5pv210-keypad";
- reg = <0x100A0000 0x100>;
- interrupts = <0 109 0>;
- };
-
- sdhci@12510000 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x12510000 0x100>;
- interrupts = <0 73 0>;
- };
-
- sdhci@12520000 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x12520000 0x100>;
- interrupts = <0 74 0>;
- };
-
- sdhci@12530000 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x12530000 0x100>;
- interrupts = <0 75 0>;
- };
-
- sdhci@12540000 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x12540000 0x100>;
- interrupts = <0 76 0>;
- };
-
- serial@13800000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13800000 0x100>;
- interrupts = <0 52 0>;
- };
-
- serial@13810000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13810000 0x100>;
- interrupts = <0 53 0>;
- };
-
- serial@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <0 54 0>;
- };
-
- serial@13830000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13830000 0x100>;
- interrupts = <0 55 0>;
- };
-
- i2c@13860000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13860000 0x100>;
- interrupts = <0 58 0>;
- };
-
- i2c@13870000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13870000 0x100>;
- interrupts = <0 59 0>;
- };
-
- i2c@13880000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13880000 0x100>;
- interrupts = <0 60 0>;
- };
-
- i2c@13890000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13890000 0x100>;
- interrupts = <0 61 0>;
- };
-
- i2c@138A0000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138A0000 0x100>;
- interrupts = <0 62 0>;
- };
-
- i2c@138B0000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138B0000 0x100>;
- interrupts = <0 63 0>;
- };
-
- i2c@138C0000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138C0000 0x100>;
- interrupts = <0 64 0>;
- };
-
- i2c@138D0000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138D0000 0x100>;
- interrupts = <0 65 0>;
- };
-
- spi_0: spi@13920000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13920000 0x100>;
- interrupts = <0 66 0>;
- tx-dma-channel = <&pdma0 7>; /* preliminary */
- rx-dma-channel = <&pdma0 6>; /* preliminary */
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi_1: spi@13930000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13930000 0x100>;
- interrupts = <0 67 0>;
- tx-dma-channel = <&pdma1 7>; /* preliminary */
- rx-dma-channel = <&pdma1 6>; /* preliminary */
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi_2: spi@13940000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13940000 0x100>;
- interrupts = <0 68 0>;
- tx-dma-channel = <&pdma0 9>; /* preliminary */
- rx-dma-channel = <&pdma0 8>; /* preliminary */
- #address-cells = <1>;
- #size-cells = <0>;
+ pinctrl_0: pinctrl@11400000 {
+ compatible = "samsung,pinctrl-exynos4210";
+ reg = <0x11400000 0x1000>;
+ interrupts = <0 47 0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "arm,amba-bus";
- interrupt-parent = <&gic>;
- ranges;
+ pinctrl_1: pinctrl@11000000 {
+ compatible = "samsung,pinctrl-exynos4210";
+ reg = <0x11000000 0x1000>;
+ interrupts = <0 46 0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
- pdma0: pdma@12680000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12680000 0x1000>;
- interrupts = <0 35 0>;
+ wakup_eint: wakeup-interrupt-controller {
+ compatible = "samsung,exynos4210-wakeup-eint";
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+ <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+ <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+ <0 32 0>;
};
+ };
- pdma1: pdma@12690000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12690000 0x1000>;
- interrupts = <0 36 0>;
- };
+ pinctrl_2: pinctrl@03860000 {
+ compatible = "samsung,pinctrl-exynos4210";
+ reg = <0x03860000 0x1000>;
};
gpio-controllers {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348793c..a352df403b7 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,12 +16,19 @@
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
compatible = "samsung,smdk5250", "samsung,exynos5250";
+ aliases {
+ mshc0 = &dwmmc_0;
+ mshc1 = &dwmmc_1;
+ mshc2 = &dwmmc_2;
+ mshc3 = &dwmmc_3;
+ };
+
memory {
reg = <0x40000000 0x80000000>;
};
chosen {
- bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
};
i2c@12C60000 {
@@ -72,6 +79,56 @@
status = "disabled";
};
+ dwmmc_0: dwmmc0@12200000 {
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3 3>;
+ samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+ <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+ <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
+ <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+ <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
+ };
+ };
+
+ dwmmc_1: dwmmc1@12210000 {
+ status = "disabled";
+ };
+
+ dwmmc_2: dwmmc2@12220000 {
+ num-slots = <1>;
+ supports-highspeed;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3 3>;
+ samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+ gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+ <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+ <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
+ <&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
+ <&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
+ };
+ };
+
+ dwmmc_3: dwmmc3@12230000 {
+ status = "disabled";
+ };
+
spi_0: spi@12d20000 {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8d123..dddfd6e444d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -27,6 +27,10 @@
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
+ gsc0 = &gsc_0;
+ gsc1 = &gsc_1;
+ gsc2 = &gsc_2;
+ gsc3 = &gsc_3;
};
gic:interrupt-controller@10481000 {
@@ -182,6 +186,38 @@
#size-cells = <0>;
};
+ dwmmc0@12200000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12200000 0x1000>;
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dwmmc1@12210000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12210000 0x1000>;
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dwmmc2@12220000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12220000 0x1000>;
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dwmmc3@12230000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12230000 0x1000>;
+ interrupts = <0 78 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
@@ -460,4 +496,28 @@
#gpio-cells = <4>;
};
};
+
+ gsc_0: gsc@0x13e00000 {
+ compatible = "samsung,exynos5-gsc";
+ reg = <0x13e00000 0x1000>;
+ interrupts = <0 85 0>;
+ };
+
+ gsc_1: gsc@0x13e10000 {
+ compatible = "samsung,exynos5-gsc";
+ reg = <0x13e10000 0x1000>;
+ interrupts = <0 86 0>;
+ };
+
+ gsc_2: gsc@0x13e20000 {
+ compatible = "samsung,exynos5-gsc";
+ reg = <0x13e20000 0x1000>;
+ interrupts = <0 87 0>;
+ };
+
+ gsc_3: gsc@0x13e30000 {
+ compatible = "samsung,exynos5-gsc";
+ reg = <0x13e30000 0x1000>;
+ interrupts = <0 88 0>;
+ };
};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 9fecf1ae777..0c6fc34821f 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -121,6 +121,10 @@
compatible = "calxeda,hb-ahci";
reg = <0xffe08000 0x10000>;
interrupts = <0 83 4>;
+ calxeda,port-phys = <&combophy5 0 &combophy0 0
+ &combophy0 1 &combophy0 2
+ &combophy0 3>;
+ dma-coherent;
};
sdhci@ffe0e000 {
@@ -306,5 +310,19 @@
reg = <0xfff51000 0x1000>;
interrupts = <0 80 4 0 81 4 0 82 4>;
};
+
+ combophy0: combo-phy@fff58000 {
+ compatible = "calxeda,hb-combophy";
+ #phy-cells = <1>;
+ reg = <0xfff58000 0x1000>;
+ phydev = <5>;
+ };
+
+ combophy5: combo-phy@fff5d000 {
+ compatible = "calxeda,hb-combophy";
+ #phy-cells = <1>;
+ reg = <0xfff5d000 0x1000>;
+ phydev = <31>;
+ };
};
};
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
new file mode 100644
index 00000000000..2131d77dc9c
--- /dev/null
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2012 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "dbx5x0.dtsi"
+
+/ {
+ model = "ST-Ericsson HREF platform with Device Tree";
+ compatible = "st-ericsson,hrefv60+";
+
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+
+ soc-u9500 {
+ uart@80120000 {
+ status = "okay";
+ };
+
+ uart@80121000 {
+ status = "okay";
+ };
+
+ uart@80007000 {
+ status = "okay";
+ };
+
+ i2c@80004000 {
+ tc3589x@42 {
+ compatible = "tc3589x";
+ reg = <0x42>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <25 0x1>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ tc3589x_gpio: tc3589x_gpio {
+ compatible = "tc3589x-gpio";
+ interrupts = <0 0x1>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ tps61052@33 {
+ compatible = "tps61052";
+ reg = <0x33>;
+ };
+ };
+
+ i2c@80128000 {
+ lp5521@0x33 {
+ compatible = "lp5521";
+ reg = <0x33>;
+ };
+
+ lp5521@0x34 {
+ compatible = "lp5521";
+ reg = <0x34>;
+ };
+
+ bh1780@0x29 {
+ compatible = "rohm,bh1780gli";
+ reg = <0x33>;
+ };
+ };
+
+ sound {
+ compatible = "stericsson,snd-soc-mop500";
+
+ stericsson,cpu-dai = <&msp1 &msp3>;
+ stericsson,audio-codec = <&codec>;
+ };
+
+ msp1: msp@80124000 {
+ status = "okay";
+ };
+
+ msp3: msp@80125000 {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index e3486f486b4..035c13f9d3c 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -42,12 +42,13 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog-gpios@0 {
+ hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
+ 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 20912b1d889..384d8b66f33 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -31,6 +31,22 @@
bus-width = <4>;
status = "okay";
};
+
+ pinctrl@80018000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
+ 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+ };
};
apbx@80040000 {
@@ -39,6 +55,47 @@
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
+
+ auart0: serial@8006c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+ };
+
+ usbphy0: usbphy@8007c000 {
+ status = "okay";
+ };
+ };
+ };
+
+ ahb@80080000 {
+ usb0: usb@80080000 {
+ vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_usb0_vbus: usb0_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
+ gpio = <&gpio0 17 0>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user {
+ label = "green";
+ gpios = <&gpio2 1 0>;
+ linux,default-trigger = "default-on";
};
};
};
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 757a327ff3e..85c3864b6a5 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -36,7 +36,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog-gpios@0 {
+ hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index e6138310e5c..9ca4ca70c1b 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -43,7 +43,7 @@
ranges;
icoll: interrupt-controller@80000000 {
- compatible = "fsl,imx23-icoll", "fsl,mxs-icoll";
+ compatible = "fsl,imx23-icoll", "fsl,icoll";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x80000000 0x2000>;
@@ -52,6 +52,7 @@
dma-apbh@80004000 {
compatible = "fsl,imx23-dma-apbh";
reg = <0x80004000 0x2000>;
+ clocks = <&clks 15>;
};
ecc@80008000 {
@@ -67,6 +68,7 @@
reg-names = "gpmi-nand", "bch";
interrupts = <13>, <56>;
interrupt-names = "gpmi-dma", "bch";
+ clocks = <&clks 34>;
fsl,gpmi-dma-channel = <4>;
status = "disabled";
};
@@ -74,6 +76,7 @@
ssp0: ssp@80010000 {
reg = <0x80010000 0x2000>;
interrupts = <15 14>;
+ clocks = <&clks 33>;
fsl,ssp-dma-channel = <1>;
status = "disabled";
};
@@ -140,6 +143,17 @@
fsl,pull-up = <0>;
};
+ auart0_2pins_a: auart0-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
+ 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
gpmi_pins_a: gpmi-nand@0 {
reg = <0>;
fsl,pinmux-ids = <
@@ -183,7 +197,6 @@
0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
- 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
>;
fsl,drive-strength = <1>;
@@ -280,6 +293,7 @@
dma-apbx@80024000 {
compatible = "fsl,imx23-dma-apbx";
reg = <0x80024000 0x2000>;
+ clocks = <&clks 16>;
};
dcp@80028000 {
@@ -306,12 +320,14 @@
compatible = "fsl,imx23-lcdif";
reg = <0x80030000 2000>;
interrupts = <46 45>;
+ clocks = <&clks 38>;
status = "disabled";
};
ssp1: ssp@80034000 {
reg = <0x80034000 0x2000>;
interrupts = <2 20>;
+ clocks = <&clks 33>;
fsl,ssp-dma-channel = <2>;
status = "disabled";
};
@@ -329,9 +345,10 @@
reg = <0x80040000 0x40000>;
ranges;
- clkctl@80040000 {
+ clks: clkctrl@80040000 {
+ compatible = "fsl,imx23-clkctrl";
reg = <0x80040000 0x2000>;
- status = "disabled";
+ #clock-cells = <1>;
};
saif0: saif@80042000 {
@@ -383,20 +400,23 @@
pwm: pwm@80064000 {
compatible = "fsl,imx23-pwm";
reg = <0x80064000 0x2000>;
+ clocks = <&clks 30>;
#pwm-cells = <2>;
fsl,pwm-number = <5>;
status = "disabled";
};
timrot@80068000 {
+ compatible = "fsl,imx23-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
- status = "disabled";
+ interrupts = <28 29 30 31>;
};
auart0: serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
+ clocks = <&clks 32>;
status = "disabled";
};
@@ -404,6 +424,7 @@
compatible = "fsl,imx23-auart";
reg = <0x8006e000 0x2000>;
interrupts = <59 60 58>;
+ clocks = <&clks 32>;
status = "disabled";
};
@@ -411,11 +432,15 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x80070000 0x2000>;
interrupts = <0>;
+ clocks = <&clks 32>, <&clks 16>;
+ clock-names = "uart", "apb_pclk";
status = "disabled";
};
- usbphy@8007c000 {
+ usbphy0: usbphy@8007c000 {
+ compatible = "fsl,imx23-usbphy";
reg = <0x8007c000 0x2000>;
+ clocks = <&clks 41>;
status = "disabled";
};
};
@@ -428,8 +453,12 @@
reg = <0x80080000 0x80000>;
ranges;
- usbctrl@80080000 {
+ usb0: usb@80080000 {
+ compatible = "fsl,imx23-usb", "fsl,imx27-usb";
reg = <0x80080000 0x40000>;
+ interrupts = <11>;
+ fsl,usbphy = <&usbphy0>;
+ clocks = <&clks 40>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 2b0ff60247a..af50469e34b 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -23,10 +23,6 @@
soc {
aipi@10000000 { /* aipi */
- wdog@10002000 {
- status = "okay";
- };
-
serial@1000a000 {
fsl,uart-has-rtscts;
status = "okay";
@@ -49,7 +45,7 @@
i2c@1001d000 {
clock-frequency = <400000>;
status = "okay";
- at24@4c {
+ at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 5303ab680a3..3e54f149884 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -62,7 +62,6 @@
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
reg = <0x10002000 0x4000>;
interrupts = <27>;
- status = "disabled";
};
uart1: serial@1000a000 {
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index b383417a558..5171667a776 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -37,7 +37,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog-gpios@0 {
+ hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
new file mode 100644
index 00000000000..05c892e931e
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+
+/ {
+ model = "Crystalfontz CFA-10049 Board";
+ compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
+
+ apb@80000000 {
+ apbh@80000000 {
+ pinctrl@80018000 {
+ spi3_pins_cfa10049: spi3-cfa10049@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
+ 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
+ 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
+ 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+ };
+
+ ssp3: ssp@80016000 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins_cfa10049>;
+ status = "okay";
+
+ gpio5: gpio5@0 {
+ compatible = "fairchild,74hc595";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0>;
+ registers-number = <2>;
+ spi-max-frequency = <100000>;
+ };
+
+ gpio6: gpio6@1 {
+ compatible = "fairchild,74hc595";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <1>;
+ registers-number = <4>;
+ spi-max-frequency = <100000>;
+ };
+
+ };
+ };
+
+ apbx@80040000 {
+ i2c1: i2c@8005a000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+ };
+
+ usbphy1: usbphy@8007e000 {
+ status = "okay";
+ };
+ };
+ };
+
+ ahb@80080000 {
+ usb1: usb@80090000 {
+ vbus-supply = <&reg_usb1_vbus>;
+ pinctrl-0 = <&usbphy1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_usb1_vbus: usb1_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio0 7 1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 773c0e84d1f..a0ad71ca3a4 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -46,11 +46,28 @@
wp-gpios = <&gpio0 28 0>;
};
+ ssp2: ssp@80014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25vf016b";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+ };
+ };
+
pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog-gpios@0 {
+ hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
@@ -128,6 +145,10 @@
status = "okay";
};
+ lradc@80050000 {
+ status = "okay";
+ };
+
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
@@ -140,6 +161,12 @@
VDDIO-supply = <&reg_3p3v>;
};
+
+ at24@51 {
+ compatible = "at24,24c32";
+ pagesize = <32>;
+ reg = <0x51>;
+ };
};
pwm: pwm@80064000 {
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 183a3fd2d85..3bab6b00c52 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -23,6 +23,8 @@
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
status = "okay";
@@ -61,19 +63,40 @@
&mmc0_cd_cfg
&mmc0_sck_cfg>;
bus-width = <8>;
- wp-gpios = <&gpio3 10 1>;
+ wp-gpios = <&gpio3 10 0>;
+ vmmc-supply = <&reg_vddio_sd0>;
status = "okay";
};
+ ssp2: ssp@80014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+ };
+ };
+
pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog-gpios@0 {
+ hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
+ 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
+ 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
+ 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
@@ -129,6 +152,7 @@
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
+ clock-frequency = <400000>;
status = "okay";
sgtl5000: codec@0a {
@@ -151,32 +175,51 @@
};
};
+ lradc@80050000 {
+ status = "okay";
+ };
+
duart: serial@80074000 {
pinctrl-names = "default";
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_2pins_a>;
+ usbphy0: usbphy@8007c000 {
status = "okay";
};
- auart3: serial@80070000 {
+ usbphy1: usbphy@8007e000 {
+ status = "okay";
+ };
+
+ auart0: serial@8006a000 {
pinctrl-names = "default";
- pinctrl-0 = <&auart3_pins_a>;
+ pinctrl-0 = <&auart0_2pins_a>;
status = "okay";
};
};
};
ahb@80080000 {
+ usb0: usb@80080000 {
+ vbus-supply = <&reg_usb0_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbphy0_pins_a>;
+ status = "okay";
+ };
+
+ usb1: usb@80090000 {
+ vbus-supply = <&reg_usb1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbphy1_pins_a>;
+ status = "okay";
+ };
+
mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
- phy-reset-gpios = <&gpio3 11 0>;
status = "okay";
};
@@ -198,6 +241,30 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
+
+ reg_vddio_sd0: vddio-sd0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio-sd0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 28 0>;
+ };
+
+ reg_usb0_vbus: usb0_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 12 0>;
+ };
+
+ reg_usb1_vbus: usb1_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 13 0>;
+ };
};
sound {
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 62bf767409a..37be532f005 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -25,7 +25,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog-gpios@0 {
+ hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
@@ -34,6 +34,24 @@
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
+
+ mac0_pins_gpio: mac0-gpio-mode@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
+ 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
+ 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
+ 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
+ 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
+ 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
+ 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
+ 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
+ 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
};
};
@@ -72,8 +90,9 @@
ahb@80080000 {
mac0: ethernet@800f0000 {
phy-mode = "rmii";
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio_mode";
pinctrl-0 = <&mac0_pins_a>;
+ pinctrl-1 = <&mac0_pins_gpio>;
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 3fa6d190fab..59fbfba23df 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -27,6 +27,8 @@
serial2 = &auart2;
serial3 = &auart3;
serial4 = &auart4;
+ ethernet0 = &mac0;
+ ethernet1 = &mac1;
};
cpus {
@@ -50,7 +52,7 @@
ranges;
icoll: interrupt-controller@80000000 {
- compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
+ compatible = "fsl,imx28-icoll", "fsl,icoll";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x80000000 0x2000>;
@@ -65,6 +67,7 @@
dma-apbh@80004000 {
compatible = "fsl,imx28-dma-apbh";
reg = <0x80004000 0x2000>;
+ clocks = <&clks 25>;
};
perfmon@80006000 {
@@ -81,34 +84,47 @@
reg-names = "gpmi-nand", "bch";
interrupts = <88>, <41>;
interrupt-names = "gpmi-dma", "bch";
+ clocks = <&clks 50>;
fsl,gpmi-dma-channel = <4>;
status = "disabled";
};
ssp0: ssp@80010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x80010000 0x2000>;
interrupts = <96 82>;
+ clocks = <&clks 46>;
fsl,ssp-dma-channel = <0>;
status = "disabled";
};
ssp1: ssp@80012000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x80012000 0x2000>;
interrupts = <97 83>;
+ clocks = <&clks 47>;
fsl,ssp-dma-channel = <1>;
status = "disabled";
};
ssp2: ssp@80014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x80014000 0x2000>;
interrupts = <98 84>;
+ clocks = <&clks 48>;
fsl,ssp-dma-channel = <2>;
status = "disabled";
};
ssp3: ssp@80016000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x80016000 0x2000>;
interrupts = <99 85>;
+ clocks = <&clks 49>;
fsl,ssp-dma-channel = <3>;
status = "disabled";
};
@@ -410,6 +426,28 @@
fsl,pull-up = <1>;
};
+ i2c0_pins_b: i2c0@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
+ 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
+ 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
saif0_pins_a: saif0@0 {
reg = <0>;
fsl,pinmux-ids = <
@@ -453,6 +491,16 @@
fsl,pull-up = <0>;
};
+ pwm4_pins_a: pwm4@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
lcdif_24bit_pins_a: lcdif-24bit@0 {
reg = <0>;
fsl,pinmux-ids = <
@@ -507,6 +555,49 @@
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
+
+ spi2_pins_a: spi2@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
+ 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
+ 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
+ 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ usbphy0_pins_a: usbphy0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
+ >;
+ fsl,drive-strength = <2>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ usbphy0_pins_b: usbphy0@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
+ >;
+ fsl,drive-strength = <2>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ usbphy1_pins_a: usbphy1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
+ >;
+ fsl,drive-strength = <2>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
};
digctl@8001c000 {
@@ -523,6 +614,7 @@
dma-apbx@80024000 {
compatible = "fsl,imx28-dma-apbx";
reg = <0x80024000 0x2000>;
+ clocks = <&clks 26>;
};
dcp@80028000 {
@@ -551,6 +643,7 @@
compatible = "fsl,imx28-lcdif";
reg = <0x80030000 0x2000>;
interrupts = <38 86>;
+ clocks = <&clks 55>;
status = "disabled";
};
@@ -558,6 +651,8 @@
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
reg = <0x80032000 0x2000>;
interrupts = <8>;
+ clocks = <&clks 58>, <&clks 58>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -565,6 +660,8 @@
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
reg = <0x80034000 0x2000>;
interrupts = <9>;
+ clocks = <&clks 59>, <&clks 59>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -611,15 +708,17 @@
reg = <0x80040000 0x40000>;
ranges;
- clkctl@80040000 {
+ clks: clkctrl@80040000 {
+ compatible = "fsl,imx28-clkctrl";
reg = <0x80040000 0x2000>;
- status = "disabled";
+ #clock-cells = <1>;
};
saif0: saif@80042000 {
compatible = "fsl,imx28-saif";
reg = <0x80042000 0x2000>;
interrupts = <59 80>;
+ clocks = <&clks 53>;
fsl,saif-dma-channel = <4>;
status = "disabled";
};
@@ -633,12 +732,16 @@
compatible = "fsl,imx28-saif";
reg = <0x80046000 0x2000>;
interrupts = <58 81>;
+ clocks = <&clks 54>;
fsl,saif-dma-channel = <5>;
status = "disabled";
};
lradc@80050000 {
+ compatible = "fsl,imx28-lradc";
reg = <0x80050000 0x2000>;
+ interrupts = <10 14 15 16 17 18 19
+ 20 21 22 23 24 25>;
status = "disabled";
};
@@ -677,20 +780,23 @@
pwm: pwm@80064000 {
compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
reg = <0x80064000 0x2000>;
+ clocks = <&clks 44>;
#pwm-cells = <2>;
fsl,pwm-number = <8>;
status = "disabled";
};
timrot@80068000 {
+ compatible = "fsl,imx28-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
- status = "disabled";
+ interrupts = <48 49 50 51>;
};
auart0: serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
+ clocks = <&clks 45>;
status = "disabled";
};
@@ -698,6 +804,7 @@
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <113 72 73>;
+ clocks = <&clks 45>;
status = "disabled";
};
@@ -705,6 +812,7 @@
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006e000 0x2000>;
interrupts = <114 74 75>;
+ clocks = <&clks 45>;
status = "disabled";
};
@@ -712,6 +820,7 @@
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x80070000 0x2000>;
interrupts = <115 76 77>;
+ clocks = <&clks 45>;
status = "disabled";
};
@@ -719,6 +828,7 @@
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x80072000 0x2000>;
interrupts = <116 78 79>;
+ clocks = <&clks 45>;
status = "disabled";
};
@@ -726,18 +836,22 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x80074000 0x1000>;
interrupts = <47>;
+ clocks = <&clks 45>, <&clks 26>;
+ clock-names = "uart", "apb_pclk";
status = "disabled";
};
usbphy0: usbphy@8007c000 {
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
reg = <0x8007c000 0x2000>;
+ clocks = <&clks 62>;
status = "disabled";
};
usbphy1: usbphy@8007e000 {
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
reg = <0x8007e000 0x2000>;
+ clocks = <&clks 63>;
status = "disabled";
};
};
@@ -754,6 +868,7 @@
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
reg = <0x80080000 0x10000>;
interrupts = <93>;
+ clocks = <&clks 60>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
};
@@ -762,6 +877,7 @@
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
reg = <0x80090000 0x10000>;
interrupts = <92>;
+ clocks = <&clks 61>;
fsl,usbphy = <&usbphy1>;
status = "disabled";
};
@@ -775,6 +891,8 @@
compatible = "fsl,imx28-fec";
reg = <0x800f0000 0x4000>;
interrupts = <101>;
+ clocks = <&clks 57>, <&clks 57>;
+ clock-names = "ipg", "ahb";
status = "disabled";
};
@@ -782,6 +900,8 @@
compatible = "fsl,imx28-fec";
reg = <0x800f4000 0x4000>;
interrupts = <102>;
+ clocks = <&clks 57>, <&clks 57>;
+ clock-names = "ipg", "ahb";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index cd86177a3ea..cbd2b1c7487 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,23 +25,31 @@
aips@70000000 { /* aips-1 */
spba@70000000 {
esdhc@70004000 { /* ESDHC1 */
- fsl,cd-internal;
- fsl,wp-internal;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1_1>;
+ fsl,cd-controller;
+ fsl,wp-controller;
status = "okay";
};
esdhc@70008000 { /* ESDHC2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc2_1>;
cd-gpios = <&gpio1 6 0>;
wp-gpios = <&gpio1 5 0>;
status = "okay";
};
uart3: serial@7000c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@70010000 { /* ECSPI1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
status = "okay";
@@ -169,31 +177,43 @@
};
};
- wdog@73f98000 { /* WDOG1 */
- status = "okay";
- };
-
iomuxc@73fa8000 {
- compatible = "fsl,imx51-iomuxc-babbage";
- reg = <0x73fa8000 0x4000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ hog {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
+ 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
+ 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
+ 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
+ 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
+ 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
+ 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
+ >;
+ };
+ };
};
uart1: serial@73fbc000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1>;
fsl,uart-has-rtscts;
status = "okay";
};
uart2: serial@73fc0000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
};
aips@80000000 { /* aips-2 */
- sdma@83fb0000 {
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
- };
-
i2c@83fc4000 { /* I2C2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
@@ -206,10 +226,14 @@
};
audmux@83fd0000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
ethernet@83fec000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "mii";
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aaa0c0a4ca8..75d069fcf89 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -130,6 +130,34 @@
};
};
+ usb@73f80000 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80000 0x0200>;
+ interrupts = <18>;
+ status = "disabled";
+ };
+
+ usb@73f80200 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80200 0x0200>;
+ interrupts = <14>;
+ status = "disabled";
+ };
+
+ usb@73f80400 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80400 0x0200>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+
+ usb@73f80600 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80600 0x0200>;
+ interrupts = <17>;
+ status = "disabled";
+ };
+
gpio1: gpio@73f84000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f84000 0x4000>;
@@ -174,7 +202,6 @@
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
interrupts = <58>;
- status = "disabled";
};
wdog@73f9c000 { /* WDOG2 */
@@ -184,6 +211,122 @@
status = "disabled";
};
+ iomuxc@73fa8000 {
+ compatible = "fsl,imx51-iomuxc";
+ reg = <0x73fa8000 0x4000>;
+
+ audmux {
+ pinctrl_audmux_1: audmuxgrp-1 {
+ fsl,pins = <
+ 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
+ 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
+ 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
+ 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
+ >;
+ };
+ };
+
+ fec {
+ pinctrl_fec_1: fecgrp-1 {
+ fsl,pins = <
+ 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
+ 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
+ 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
+ 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
+ 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
+ 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
+ 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
+ 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
+ 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
+ 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
+ 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
+ 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
+ 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
+ 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
+ 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
+ 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
+ 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
+ >;
+ };
+ };
+
+ ecspi1 {
+ pinctrl_ecspi1_1: ecspi1grp-1 {
+ fsl,pins = <
+ 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
+ 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
+ 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
+ >;
+ };
+ };
+
+ esdhc1 {
+ pinctrl_esdhc1_1: esdhc1grp-1 {
+ fsl,pins = <
+ 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
+ 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
+ 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
+ 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
+ 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
+ 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
+ >;
+ };
+ };
+
+ esdhc2 {
+ pinctrl_esdhc2_1: esdhc2grp-1 {
+ fsl,pins = <
+ 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
+ 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
+ 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
+ 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
+ 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
+ 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
+ >;
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2_1: i2c2grp-1 {
+ fsl,pins = <
+ 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
+ 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
+ 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
+ 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
+ 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
+ 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_1: uart3grp-1 {
+ fsl,pins = <
+ 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
+ 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
+ 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
+ 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
+ >;
+ };
+ };
+ };
+
uart1: serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
@@ -219,6 +362,7 @@
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
cspi@83fc0000 {
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index da895e93a99..4be76f22352 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -25,31 +25,66 @@
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1_2>;
cd-gpios = <&gpio1 1 0>;
wp-gpios = <&gpio1 9 0>;
status = "okay";
};
};
- wdog@53f98000 { /* WDOG1 */
- status = "okay";
- };
-
iomuxc@53fa8000 {
- compatible = "fsl,imx53-iomuxc-ard";
- reg = <0x53fa8000 0x4000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ hog {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
+ 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
+ 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
+ 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
+ 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
+ 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
+ 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
+ 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
+ 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
+ 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
+ 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
+ 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
+ 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
+ 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
+ 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
+ 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
+ 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
+ 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
+ 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
+ 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
+ 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
+ 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
+ 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
+ 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
+ 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
+ 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
+ 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
+ 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
+ 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
+ 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
+ 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
+ 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
+ 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
+ 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
+ >;
+ };
+ };
};
uart1: serial@53fbc000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_2>;
status = "okay";
};
};
-
- aips@60000000 { /* AIPS2 */
- sdma@63fb0000 {
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
- };
- };
};
eim-cs1@f4000000 {
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 9c798034675..a124d1e2525 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -25,12 +25,16 @@
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio3 14 0>;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
@@ -56,32 +60,45 @@
};
esdhc@50020000 { /* ESDHC3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
- wdog@53f98000 { /* WDOG1 */
- status = "okay";
- };
-
iomuxc@53fa8000 {
- compatible = "fsl,imx53-iomuxc-evk";
- reg = <0x53fa8000 0x4000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ hog {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+ 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+ 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+ 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+ 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+ 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
+ 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+ 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+ >;
+ };
+ };
};
uart1: serial@53fbc000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
- sdma@63fb0000 {
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
- };
-
i2c@63fc4000 { /* I2C2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
pmic: mc13892@08 {
@@ -96,6 +113,8 @@
};
ethernet@63fec000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 2d803a9a694..08948af86d1 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -25,6 +25,8 @@
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
status = "okay";
};
@@ -35,32 +37,46 @@
};
esdhc@50020000 { /* ESDHC3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
- wdog@53f98000 { /* WDOG1 */
- status = "okay";
- };
-
iomuxc@53fa8000 {
- compatible = "fsl,imx53-iomuxc-qsb";
- reg = <0x53fa8000 0x4000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ hog {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
+ 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
+ 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+ 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+ 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+ 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+ 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+ 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+ 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+ >;
+ };
+ };
};
uart1: serial@53fbc000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
- sdma@63fb0000 {
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
- };
-
i2c@63fc4000 { /* I2C2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
@@ -72,6 +88,8 @@
};
i2c@63fc8000 { /* I2C1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
@@ -158,10 +176,14 @@
};
audmux@63fd0000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
ethernet@63fec000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 08091029168..06c68580c84 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -25,22 +25,30 @@
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio4 11 0>;
status = "okay";
};
esdhc@50008000 { /* ESDHC2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc2_1>;
non-removable;
status = "okay";
};
uart3: serial@5000c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
@@ -72,35 +80,49 @@
};
esdhc@50020000 { /* ESDHC3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc3_1>;
non-removable;
status = "okay";
};
};
- wdog@53f98000 { /* WDOG1 */
- status = "okay";
- };
-
iomuxc@53fa8000 {
- compatible = "fsl,imx53-iomuxc-smd";
- reg = <0x53fa8000 0x4000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ hog {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+ 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+ 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+ 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+ 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+ 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
+ 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+ >;
+ };
+ };
};
uart1: serial@53fbc000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
uart2: serial@53fc0000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
- sdma@63fb0000 {
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
- };
-
i2c@63fc4000 { /* I2C2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
codec: sgtl5000@0a {
@@ -120,6 +142,8 @@
};
i2c@63fc8000 { /* I2C1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
@@ -139,6 +163,8 @@
};
ethernet@63fec000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index dc00c62acc8..76ebb1ad267 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,6 +135,34 @@
};
};
+ usb@53f80000 {
+ compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+ reg = <0x53f80000 0x0200>;
+ interrupts = <18>;
+ status = "disabled";
+ };
+
+ usb@53f80200 {
+ compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+ reg = <0x53f80200 0x0200>;
+ interrupts = <14>;
+ status = "disabled";
+ };
+
+ usb@53f80400 {
+ compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+ reg = <0x53f80400 0x0200>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+
+ usb@53f80600 {
+ compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+ reg = <0x53f80600 0x0200>;
+ interrupts = <17>;
+ status = "disabled";
+ };
+
gpio1: gpio@53f84000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53f84000 0x4000>;
@@ -179,7 +207,6 @@
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
- status = "disabled";
};
wdog@53f9c000 { /* WDOG2 */
@@ -189,6 +216,161 @@
status = "disabled";
};
+ iomuxc@53fa8000 {
+ compatible = "fsl,imx53-iomuxc";
+ reg = <0x53fa8000 0x4000>;
+
+ audmux {
+ pinctrl_audmux_1: audmuxgrp-1 {
+ fsl,pins = <
+ 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
+ 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
+ 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
+ 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
+ >;
+ };
+ };
+
+ fec {
+ pinctrl_fec_1: fecgrp-1 {
+ fsl,pins = <
+ 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
+ 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
+ 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
+ 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
+ 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
+ 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
+ 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
+ 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
+ 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
+ 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
+ >;
+ };
+ };
+
+ ecspi1 {
+ pinctrl_ecspi1_1: ecspi1grp-1 {
+ fsl,pins = <
+ 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
+ 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
+ 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
+ >;
+ };
+ };
+
+ esdhc1 {
+ pinctrl_esdhc1_1: esdhc1grp-1 {
+ fsl,pins = <
+ 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+ 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+ 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+ 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+ 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+ 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+ >;
+ };
+
+ pinctrl_esdhc1_2: esdhc1grp-2 {
+ fsl,pins = <
+ 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+ 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+ 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+ 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+ 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
+ 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
+ 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
+ 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
+ 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+ 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+ >;
+ };
+ };
+
+ esdhc2 {
+ pinctrl_esdhc2_1: esdhc2grp-1 {
+ fsl,pins = <
+ 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
+ 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
+ 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
+ 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
+ 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
+ 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
+ >;
+ };
+ };
+
+ esdhc3 {
+ pinctrl_esdhc3_1: esdhc3grp-1 {
+ fsl,pins = <
+ 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
+ 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
+ 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
+ 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
+ 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
+ 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
+ 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
+ 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
+ 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
+ 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
+ >;
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
+ 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
+ >;
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2_1: i2c2grp-1 {
+ fsl,pins = <
+ 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
+ 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
+ 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
+ >;
+ };
+
+ pinctrl_uart1_2: uart1grp-2 {
+ fsl,pins = <
+ 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
+ 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
+ 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_1: uart3grp-1 {
+ fsl,pins = <
+ 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
+ 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
+ 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
+ 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
+ >;
+ };
+ };
+ };
+
uart1: serial@53fbc000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
@@ -203,6 +385,20 @@
status = "disabled";
};
+ can1: can@53fc8000 {
+ compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+ reg = <0x53fc8000 0x4000>;
+ interrupts = <82>;
+ status = "disabled";
+ };
+
+ can2: can@53fcc000 {
+ compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+ reg = <0x53fcc000 0x4000>;
+ interrupts = <83>;
+ status = "disabled";
+ };
+
gpio5: gpio@53fdc000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53fdc000 0x4000>;
@@ -277,6 +473,7 @@
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
cspi@63fc0000 {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d792581672c..15df4c105e8 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -28,8 +28,27 @@
status = "disabled"; /* gpmi nand conflicts with SD */
};
+ aips-bus@02000000 { /* AIPS1 */
+ iomuxc@020e0000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ hog {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+ 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
+ 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+ >;
+ };
+ };
+ };
+ };
+
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_2>;
phy-mode = "rgmii";
status = "okay";
};
@@ -52,6 +71,8 @@
};
uart4: serial@021f0000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4_1>;
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3e617..d152328285a 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -46,15 +46,20 @@
iomuxc@020e0000 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_hog>;
+ pinctrl-0 = <&pinctrl_hog>;
- gpios {
- pinctrl_gpio_hog: gpiohog {
+ hog {
+ pinctrl_hog: hoggrp {
fsl,pins = <
- 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
- 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
- 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
- >;
+ 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
+ 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
+ 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+ 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+ 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
+ 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
+ 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
+ 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+ >;
};
};
};
@@ -63,6 +68,9 @@
aips-bus@02100000 { /* AIPS2 */
usb@02184000 { /* USB OTG */
vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg_1>;
+ disable-over-current;
status = "okay";
};
@@ -71,12 +79,16 @@
};
ethernet@02188000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3_2>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
@@ -84,6 +96,8 @@
};
usdhc@0219c000 { /* uSDHC4 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4_2>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <&reg_3p3v>;
@@ -99,7 +113,7 @@
uart2: serial@021e8000 {
status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial2_1>;
+ pinctrl-0 = <&pinctrl_uart2_1>;
};
i2c@021a0000 { /* I2C1 */
@@ -111,6 +125,7 @@
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ clocks = <&clks 169>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 07509a18117..e596c28c214 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -22,28 +22,51 @@
};
soc {
-
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
uart1: serial@02020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
+
+ iomuxc@020e0000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ hog {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
+ 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
+ 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
+ 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
+ >;
+ };
+ };
+ };
};
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
status = "okay";
};
usdhc@02194000 { /* uSDHC2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_1>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079f71a..f3990b04fec 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -97,18 +97,23 @@
dma-apbh@00110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x00110000 0x2000>;
+ clocks = <&clks 106>;
};
gpmi-nand@00112000 {
- compatible = "fsl,imx6q-gpmi-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
- reg-names = "gpmi-nand", "bch";
- interrupts = <0 13 0x04>, <0 15 0x04>;
- interrupt-names = "gpmi-dma", "bch";
- fsl,gpmi-dma-channel = <0>;
- status = "disabled";
+ compatible = "fsl,imx6q-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <0 13 0x04>, <0 15 0x04>;
+ interrupt-names = "gpmi-dma", "bch";
+ clocks = <&clks 152>, <&clks 153>, <&clks 151>,
+ <&clks 150>, <&clks 149>;
+ clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+ fsl,gpmi-dma-channel = <0>;
+ status = "disabled";
};
timer@00a00600 {
@@ -150,6 +155,8 @@
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <0 31 0x04>;
+ clocks = <&clks 112>, <&clks 112>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -159,6 +166,8 @@
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <0 32 0x04>;
+ clocks = <&clks 113>, <&clks 113>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -168,6 +177,8 @@
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <0 33 0x04>;
+ clocks = <&clks 114>, <&clks 114>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -177,6 +188,8 @@
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <0 34 0x04>;
+ clocks = <&clks 115>, <&clks 115>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -186,6 +199,8 @@
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02018000 0x4000>;
interrupts = <0 35 0x04>;
+ clocks = <&clks 116>, <&clks 116>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -193,6 +208,8 @@
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -205,6 +222,7 @@
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 0x04>;
+ clocks = <&clks 178>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <38 37>;
status = "disabled";
@@ -214,6 +232,7 @@
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 0x04>;
+ clocks = <&clks 179>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <42 41>;
status = "disabled";
@@ -223,6 +242,7 @@
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 0x04>;
+ clocks = <&clks 180>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <46 45>;
status = "disabled";
@@ -362,24 +382,26 @@
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 0x04>;
- status = "disabled";
+ clocks = <&clks 0>;
};
wdog@020c0000 { /* WDOG2 */
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 0x04>;
+ clocks = <&clks 0>;
status = "disabled";
};
- ccm@020c4000 {
+ clks: ccm@020c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
+ #clock-cells = <1>;
};
- anatop@020c8000 {
- compatible = "fsl,imx6q-anatop";
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
@@ -472,12 +494,14 @@
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
+ clocks = <&clks 182>;
};
usbphy2: usbphy@020ca000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <0 45 0x04>;
+ clocks = <&clks 183>;
};
snvs@020cc000 {
@@ -507,6 +531,11 @@
interrupts = <0 89 0x04 0 90 0x04>;
};
+ gpr: iomuxc-gpr@020e0000 {
+ compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+ reg = <0x020e0000 0x38>;
+ };
+
iomuxc@020e0000 {
compatible = "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
@@ -514,86 +543,207 @@
/* shared pinctrl settings */
audmux {
pinctrl_audmux_1: audmux-1 {
- fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
- 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
- 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
- 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+ fsl,pins = <
+ 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+ 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+ 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+ 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+ >;
+ };
+ };
+
+ ecspi1 {
+ pinctrl_ecspi1_1: ecspi1grp-1 {
+ fsl,pins = <
+ 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+ 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+ 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+ >;
+ };
+ };
+
+ enet {
+ pinctrl_enet_1: enetgrp-1 {
+ fsl,pins = <
+ 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
+ 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
+ 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+ 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+ 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+ 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+ 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+ 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+ 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+ 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+ 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+ 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+ 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+ 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+ 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+ >;
+ };
+
+ pinctrl_enet_2: enetgrp-2 {
+ fsl,pins = <
+ 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
+ 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
+ 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+ 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+ 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+ 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+ 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+ 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+ 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+ 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+ 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+ 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+ 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+ 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+ 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+ >;
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
- fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
- 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
- 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
- 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
- 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
- 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
- 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
- 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
- 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
- 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
- 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
- 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
- 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
- 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
- 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
- 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
- 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
- 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
- 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+ fsl,pins = <
+ 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+ 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+ 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+ 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+ 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+ 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+ 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+ 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+ 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+ 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+ 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+ 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+ 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+ 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+ 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+ 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+ 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+ 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+ 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+ >;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
- fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
- 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+ fsl,pins = <
+ 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
+ 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
+ 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
+ >;
};
};
- serial2 {
- pinctrl_serial2_1: serial2grp-1 {
- fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
- 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
+ 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
+ >;
+ };
+ };
+
+ uart4 {
+ pinctrl_uart4_1: uart4grp-1 {
+ fsl,pins = <
+ 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
+ 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+ >;
+ };
+ };
+
+ usbotg {
+ pinctrl_usbotg_1: usbotggrp-1 {
+ fsl,pins = <
+ 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
+ >;
+ };
+ };
+
+ usdhc2 {
+ pinctrl_usdhc2_1: usdhc2grp-1 {
+ fsl,pins = <
+ 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
+ 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
+ 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
+ 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
+ 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
+ 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
+ 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
+ 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
+ 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
+ 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
+ >;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
- fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
- 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
- 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
- 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
- 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
- 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
- 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
- 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
- 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
- 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+ fsl,pins = <
+ 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+ 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+ 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+ 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+ 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+ 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+ 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
+ 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
+ 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+ 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc3_2: usdhc3grp-2 {
+ fsl,pins = <
+ 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+ 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+ 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+ 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+ 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+ 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+ >;
};
};
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
- fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
- 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
- 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
- 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
- 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
- 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
- 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
- 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
- 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
- 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+ fsl,pins = <
+ 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+ 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+ 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+ 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+ 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+ 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+ 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+ >;
};
- };
- ecspi1 {
- pinctrl_ecspi1_1: ecspi1grp-1 {
- fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
- 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
- 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+ pinctrl_usdhc4_2: usdhc4grp-2 {
+ fsl,pins = <
+ 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+ 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+ 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+ >;
};
};
};
@@ -612,6 +762,9 @@
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 0x04>;
+ clocks = <&clks 155>, <&clks 155>;
+ clock-names = "ipg", "ahb";
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
};
};
@@ -635,7 +788,9 @@
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 0x04>;
+ clocks = <&clks 162>;
fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
status = "disabled";
};
@@ -643,7 +798,9 @@
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 40 0x04>;
+ clocks = <&clks 162>;
fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
@@ -651,6 +808,8 @@
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 41 0x04>;
+ clocks = <&clks 162>;
+ fsl,usbmisc = <&usbmisc 2>;
status = "disabled";
};
@@ -658,13 +817,24 @@
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184600 0x200>;
interrupts = <0 42 0x04>;
+ clocks = <&clks 162>;
+ fsl,usbmisc = <&usbmisc 3>;
status = "disabled";
};
+ usbmisc: usbmisc@02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ clocks = <&clks 162>;
+ };
+
ethernet@02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 118 0x04 0 119 0x04>;
+ clocks = <&clks 117>, <&clks 117>;
+ clock-names = "ipg", "ahb";
status = "disabled";
};
@@ -677,6 +847,8 @@
compatible = "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 0x04>;
+ clocks = <&clks 163>, <&clks 163>, <&clks 163>;
+ clock-names = "ipg", "ahb", "per";
status = "disabled";
};
@@ -684,6 +856,8 @@
compatible = "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 0x04>;
+ clocks = <&clks 164>, <&clks 164>, <&clks 164>;
+ clock-names = "ipg", "ahb", "per";
status = "disabled";
};
@@ -691,6 +865,8 @@
compatible = "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 0x04>;
+ clocks = <&clks 165>, <&clks 165>, <&clks 165>;
+ clock-names = "ipg", "ahb", "per";
status = "disabled";
};
@@ -698,6 +874,8 @@
compatible = "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 0x04>;
+ clocks = <&clks 166>, <&clks 166>, <&clks 166>;
+ clock-names = "ipg", "ahb", "per";
status = "disabled";
};
@@ -707,6 +885,7 @@
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
reg = <0x021a0000 0x4000>;
interrupts = <0 36 0x04>;
+ clocks = <&clks 125>;
status = "disabled";
};
@@ -716,6 +895,7 @@
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
reg = <0x021a4000 0x4000>;
interrupts = <0 37 0x04>;
+ clocks = <&clks 126>;
status = "disabled";
};
@@ -725,6 +905,7 @@
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
reg = <0x021a8000 0x4000>;
interrupts = <0 38 0x04>;
+ clocks = <&clks 127>;
status = "disabled";
};
@@ -788,6 +969,8 @@
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <0 27 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -795,6 +978,8 @@
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <0 28 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -802,6 +987,8 @@
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <0 29 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
status = "disabled";
};
@@ -809,6 +996,8 @@
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <0 30 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
new file mode 100644
index 00000000000..813b91d7bea
--- /dev/null
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -0,0 +1,76 @@
+/*
+ * SoC core Device Tree for the ARM Integrator platforms
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ timer@13000000 {
+ reg = <0x13000000 0x100>;
+ interrupt-parent = <&pic>;
+ interrupts = <5>;
+ };
+
+ timer@13000100 {
+ reg = <0x13000100 0x100>;
+ interrupt-parent = <&pic>;
+ interrupts = <6>;
+ };
+
+ timer@13000200 {
+ reg = <0x13000200 0x100>;
+ interrupt-parent = <&pic>;
+ interrupts = <7>;
+ };
+
+ pic@14000000 {
+ compatible = "arm,versatile-fpga-irq";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0x14000000 0x100>;
+ clear-mask = <0xffffffff>;
+ };
+
+ flash@24000000 {
+ compatible = "cfi-flash";
+ reg = <0x24000000 0x02000000>;
+ };
+
+ fpga {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&pic>;
+
+ /*
+ * These PrimeCells are in the same locations and using the
+ * same interrupts in all Integrators, however the silicon
+ * version deployed is different.
+ */
+ rtc@15000000 {
+ reg = <0x15000000 0x1000>;
+ interrupts = <8>;
+ };
+
+ uart@16000000 {
+ reg = <0x16000000 0x1000>;
+ interrupts = <1>;
+ };
+
+ uart@17000000 {
+ reg = <0x17000000 0x1000>;
+ interrupts = <2>;
+ };
+
+ kmi@18000000 {
+ reg = <0x18000000 0x1000>;
+ interrupts = <3>;
+ };
+
+ kmi@19000000 {
+ reg = <0x19000000 0x1000>;
+ interrupts = <4>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
new file mode 100644
index 00000000000..61767757b50
--- /dev/null
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -0,0 +1,68 @@
+/*
+ * Device Tree for the ARM Integrator/AP platform
+ */
+
+/dts-v1/;
+/include/ "integrator.dtsi"
+
+/ {
+ model = "ARM Integrator/AP";
+ compatible = "arm,integrator-ap";
+
+ aliases {
+ arm,timer-primary = &timer2;
+ arm,timer-secondary = &timer1;
+ };
+
+ chosen {
+ bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
+ };
+
+ timer0: timer@13000000 {
+ compatible = "arm,integrator-timer";
+ };
+
+ timer1: timer@13000100 {
+ compatible = "arm,integrator-timer";
+ };
+
+ timer2: timer@13000200 {
+ compatible = "arm,integrator-timer";
+ };
+
+ pic: pic@14000000 {
+ valid-mask = <0x003fffff>;
+ };
+
+ fpga {
+ /*
+ * The Integator/AP predates the idea to have magic numbers
+ * identifying the PrimeCell in hardware, thus we have to
+ * supply these from the device tree.
+ */
+ rtc: rtc@15000000 {
+ compatible = "arm,pl030", "arm,primecell";
+ arm,primecell-periphid = <0x00041030>;
+ };
+
+ uart0: uart@16000000 {
+ compatible = "arm,pl010", "arm,primecell";
+ arm,primecell-periphid = <0x00041010>;
+ };
+
+ uart1: uart@17000000 {
+ compatible = "arm,pl010", "arm,primecell";
+ arm,primecell-periphid = <0x00041010>;
+ };
+
+ kmi0: kmi@18000000 {
+ compatible = "arm,pl050", "arm,primecell";
+ arm,primecell-periphid = <0x00041050>;
+ };
+
+ kmi1: kmi@19000000 {
+ compatible = "arm,pl050", "arm,primecell";
+ arm,primecell-periphid = <0x00041050>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
new file mode 100644
index 00000000000..2dd5e4e4848
--- /dev/null
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -0,0 +1,110 @@
+/*
+ * Device Tree for the ARM Integrator/CP platform
+ */
+
+/dts-v1/;
+/include/ "integrator.dtsi"
+
+/ {
+ model = "ARM Integrator/CP";
+ compatible = "arm,integrator-cp";
+
+ aliases {
+ arm,timer-primary = &timer2;
+ arm,timer-secondary = &timer1;
+ };
+
+ chosen {
+ bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
+ };
+
+ timer0: timer@13000000 {
+ compatible = "arm,sp804", "arm,primecell";
+ };
+
+ timer1: timer@13000100 {
+ compatible = "arm,sp804", "arm,primecell";
+ };
+
+ timer2: timer@13000200 {
+ compatible = "arm,sp804", "arm,primecell";
+ };
+
+ pic: pic@14000000 {
+ valid-mask = <0x1fc003ff>;
+ };
+
+ cic: cic@10000040 {
+ compatible = "arm,versatile-fpga-irq";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0x10000040 0x100>;
+ clear-mask = <0xffffffff>;
+ valid-mask = <0x00000007>;
+ };
+
+ sic: sic@ca000000 {
+ compatible = "arm,versatile-fpga-irq";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0xca000000 0x100>;
+ clear-mask = <0x00000fff>;
+ valid-mask = <0x00000fff>;
+ };
+
+ ethernet@c8000000 {
+ compatible = "smsc,lan91c111";
+ reg = <0xc8000000 0x10>;
+ interrupt-parent = <&pic>;
+ interrupts = <27>;
+ };
+
+ fpga {
+ /*
+ * These PrimeCells are at the same location and using
+ * the same interrupts in all Integrators, but in the CP
+ * slightly newer versions are deployed.
+ */
+ rtc@15000000 {
+ compatible = "arm,pl031", "arm,primecell";
+ };
+
+ uart@16000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ };
+
+ uart@17000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ };
+
+ kmi@18000000 {
+ compatible = "arm,pl050", "arm,primecell";
+ };
+
+ kmi@19000000 {
+ compatible = "arm,pl050", "arm,primecell";
+ };
+
+ /*
+ * These PrimeCells are only available on the Integrator/CP
+ */
+ mmc@1c000000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x1c000000 0x1000>;
+ interrupts = <23 24>;
+ max-frequency = <515633>;
+ };
+
+ aaci@1d000000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x1d000000 0x1000>;
+ interrupts = <25>;
+ };
+
+ clcd@c0000000 {
+ compatible = "arm,pl110", "arm,primecell";
+ reg = <0xC0000000 0x1000>;
+ interrupts = <22>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 7408655f91b..9b32d027282 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -25,6 +25,16 @@
};
};
+ gpio_fan {
+ /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
+ compatible = "gpio-fan";
+ gpios = <&gpio1 14 1
+ &gpio1 13 1>;
+ gpio-fan,speed-map = <0 0
+ 3000 1
+ 6000 2>;
+ };
+
ocp@f1000000 {
sata@80000 {
status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
new file mode 100644
index 00000000000..08a582414b8
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+ model = "Seagate FreeAgent Dockstar";
+ compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+ };
+
+ ocp@f1000000 {
+ serial@12000 {
+ clock-frequency = <200000000>;
+ status = "ok";
+ };
+
+ nand@3000000 {
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x0100000 0x400000>;
+ };
+
+ partition@500000 {
+ label = "data";
+ reg = <0x0500000 0xfb00000>;
+ };
+ };
+ };
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ health {
+ label = "status:green:health";
+ gpios = <&gpio1 14 1>;
+ linux,default-trigger = "default-on";
+ };
+ fault {
+ label = "status:orange:fault";
+ gpios = <&gpio1 15 1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 52d94704510..d97cd9d4753 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -12,7 +12,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
linux,initrd-start = <0x4500040>;
linux,initrd-end = <0x4800000>;
};
@@ -30,7 +30,37 @@
clock-frequency = <200000000>;
status = "ok";
};
+
+ nand@3000000 {
+ status = "okay";
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0000000 0xc0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0xa0000 0x20000>;
+ };
+
+ partition@100000 {
+ label = "zImage";
+ reg = <0x100000 0x300000>;
+ };
+
+ partition@540000 {
+ label = "initrd";
+ reg = <0x540000 0x300000>;
+ };
+
+ partition@980000 {
+ label = "boot";
+ reg = <0x980000 0x1f400000>;
+ };
+ };
};
+
gpio-leds {
compatible = "gpio-leds";
@@ -41,9 +71,13 @@
};
power-blue {
label = "power:blue";
- gpios = <&gpio1 11 0>;
+ gpios = <&gpio1 10 0>;
linux,default-trigger = "timer";
};
+ power-red {
+ label = "power:red";
+ gpios = <&gpio1 11 0>;
+ };
usb1 {
label = "usb1:blue";
gpios = <&gpio1 12 0>;
@@ -65,4 +99,22 @@
gpios = <&gpio1 16 0>;
};
};
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ button@1 {
+ label = "OTB Button";
+ linux,code = <133>;
+ gpios = <&gpio1 3 1>;
+ debounce-interval = <100>;
+ };
+ button@2 {
+ label = "Reset";
+ linux,code = <0x198>;
+ gpios = <&gpio0 12 1>;
+ debounce-interval = <100>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
new file mode 100644
index 00000000000..865aeec40a2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+ model = "Iomega StorCenter ix2-200";
+ compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+
+ ocp@f1000000 {
+ i2c@11000 {
+ status = "okay";
+
+ lm63: lm63@4c {
+ compatible = "national,lm63";
+ reg = <0x4c>;
+ };
+ };
+
+ serial@12000 {
+ clock-frequency = <200000000>;
+ status = "ok";
+ };
+
+ nand@3000000 {
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0xa0000 0x20000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x100000 0x300000>;
+ };
+
+ partition@400000 {
+ label = "uInitrd";
+ reg = <0x540000 0x1000000>;
+ };
+ };
+ sata@80000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+
+ };
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ power_led {
+ label = "status:white:power_led";
+ gpios = <&gpio0 16 0>;
+ linux,default-trigger = "default-on";
+ };
+ health_led1 {
+ label = "status:red:health_led";
+ gpios = <&gpio1 5 0>;
+ };
+ health_led2 {
+ label = "status:white:health_led";
+ gpios = <&gpio1 4 0>;
+ };
+ backup_led {
+ label = "status:blue:backup_led";
+ gpios = <&gpio0 15 0>;
+ };
+ };
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ Power {
+ label = "Power Button";
+ linux,code = <116>;
+ gpios = <&gpio0 14 1>;
+ };
+ Reset {
+ label = "Reset Button";
+ linux,code = <0x198>;
+ gpios = <&gpio0 12 1>;
+ };
+ OTB {
+ label = "OTB Button";
+ linux,code = <133>;
+ gpios = <&gpio1 3 1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
new file mode 100644
index 00000000000..75bdb93fed2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+ model = "Keymile Kirkwood Reference Design";
+ compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+
+ ocp@f1000000 {
+ serial@12000 {
+ clock-frequency = <200000000>;
+ status = "ok";
+ };
+
+ nand@3000000 {
+ status = "ok";
+ chip-delay = <25>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index cef9616f330..4e5b8154a5b 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -14,7 +14,8 @@
ocp@f1000000 {
compatible = "simple-bus";
- ranges = <0 0xf1000000 0x4000000>;
+ ranges = <0x00000000 0xf1000000 0x4000000
+ 0xf5000000 0xf5000000 0x0000400>;
#address-cells = <1>;
#size-cells = <1>;
@@ -105,5 +106,14 @@
clock-frequency = <100000>;
status = "disabled";
};
+
+ crypto@30000 {
+ compatible = "marvell,orion-crypto";
+ reg = <0x30000 0x10000>,
+ <0xf5000000 0x800>;
+ reg-names = "regs", "sram";
+ interrupts = <22>;
+ status = "okay";
+ };
};
};
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 80f74e25640..0514fb41627 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -26,6 +26,11 @@
interrupt-parent = <&intc>;
ranges;
+ L2: l2-cache {
+ compatible = "marvell,tauros2-cache";
+ marvell,tauros2-cache-features = <0x3>;
+ };
+
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 45bc4bb04e5..31f2157cd7d 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -7,7 +7,7 @@
compatible = "qcom,msm8660-surf", "qcom,msm8660";
interrupt-parent = <&intc>;
- intc: interrupt-controller@02080000 {
+ intc: interrupt-controller@2080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;
#interrupt-cells = <3>;
@@ -15,6 +15,23 @@
< 0x02081000 0x1000 >;
};
+ timer@2000004 {
+ compatible = "qcom,msm-gpt", "qcom,msm-timer";
+ interrupts = <1 1 0x301>;
+ reg = <0x02000004 0x10>;
+ clock-frequency = <32768>;
+ cpu-offset = <0x40000>;
+ };
+
+ timer@2000024 {
+ compatible = "qcom,msm-dgt", "qcom,msm-timer";
+ interrupts = <1 0 0x301>;
+ reg = <0x02000024 0x10>,
+ <0x02000034 0x4>;
+ clock-frequency = <6750000>;
+ cpu-offset = <0x40000>;
+ };
+
serial@19c400000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
new file mode 100644
index 00000000000..9e621b5ad3d
--- /dev/null
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -0,0 +1,41 @@
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "Qualcomm MSM8960 CDP";
+ compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+ interrupt-parent = <&intc>;
+
+ intc: interrupt-controller@2000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = < 0x02000000 0x1000 >,
+ < 0x02002000 0x1000 >;
+ };
+
+ timer@200a004 {
+ compatible = "qcom,msm-gpt", "qcom,msm-timer";
+ interrupts = <1 2 0x301>;
+ reg = <0x0200a004 0x10>;
+ clock-frequency = <32768>;
+ cpu-offset = <0x80000>;
+ };
+
+ timer@200a024 {
+ compatible = "qcom,msm-dgt", "qcom,msm-timer";
+ interrupts = <1 1 0x301>;
+ reg = <0x0200a024 0x10>,
+ <0x0200a034 0x4>;
+ clock-frequency = <6750000>;
+ cpu-offset = <0x80000>;
+ };
+
+ serial@19c400000 {
+ compatible = "qcom,msm-hsuart", "qcom,msm-uart";
+ reg = <0x16440000 0x1000>,
+ <0x16400000 0x1000>;
+ interrupts = <0 154 0x0>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 25b50b759de..77b84e17c47 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-/include/ "omap2.dtsi"
+/include/ "omap2420.dtsi"
/ {
model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
new file mode 100644
index 00000000000..bfd76b4a0dd
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -0,0 +1,48 @@
+/*
+ * Device Tree Source for OMAP2420 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+ compatible = "ti,omap2420", "ti,omap2";
+
+ ocp {
+ omap2420_pmx: pinmux@48000030 {
+ compatible = "ti,omap2420-padconf", "pinctrl-single";
+ reg = <0x48000030 0x0113>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <8>;
+ pinctrl-single,function-mask = <0x3f>;
+ };
+
+ mcbsp1: mcbsp@48074000 {
+ compatible = "ti,omap2420-mcbsp";
+ reg = <0x48074000 0xff>;
+ reg-names = "mpu";
+ interrupts = <59>, /* TX interrupt */
+ <60>; /* RX interrupt */
+ interrupt-names = "tx", "rx";
+ interrupt-parent = <&intc>;
+ ti,hwmods = "mcbsp1";
+ };
+
+ mcbsp2: mcbsp@48076000 {
+ compatible = "ti,omap2420-mcbsp";
+ reg = <0x48076000 0xff>;
+ reg-names = "mpu";
+ interrupts = <62>, /* TX interrupt */
+ <63>; /* RX interrupt */
+ interrupt-names = "tx", "rx";
+ interrupt-parent = <&intc>;
+ ti,hwmods = "mcbsp2";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
new file mode 100644
index 00000000000..4565d9750f4
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Device Tree Source for OMAP243x SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+ compatible = "ti,omap2430", "ti,omap2";
+
+ ocp {
+ omap2430_pmx: pinmux@49002030 {
+ compatible = "ti,omap2430-padconf", "pinctrl-single";
+ reg = <0x49002030 0x0154>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <8>;
+ pinctrl-single,function-mask = <0x3f>;
+ };
+
+ mcbsp1: mcbsp@48074000 {
+ compatible = "ti,omap2430-mcbsp";
+ reg = <0x48074000 0xff>;
+ reg-names = "mpu";
+ interrupts = <64>, /* OCP compliant interrupt */
+ <59>, /* TX interrupt */
+ <60>, /* RX interrupt */
+ <61>; /* RX overflow interrupt */
+ interrupt-names = "common", "tx", "rx", "rx_overflow";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp1";
+ };
+
+ mcbsp2: mcbsp@48076000 {
+ compatible = "ti,omap2430-mcbsp";
+ reg = <0x48076000 0xff>;
+ reg-names = "mpu";
+ interrupts = <16>, /* OCP compliant interrupt */
+ <62>, /* TX interrupt */
+ <63>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp2";
+ };
+
+ mcbsp3: mcbsp@4808c000 {
+ compatible = "ti,omap2430-mcbsp";
+ reg = <0x4808c000 0xff>;
+ reg-names = "mpu";
+ interrupts = <17>, /* OCP compliant interrupt */
+ <89>, /* TX interrupt */
+ <90>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp3";
+ };
+
+ mcbsp4: mcbsp@4808e000 {
+ compatible = "ti,omap2430-mcbsp";
+ reg = <0x4808e000 0xff>;
+ reg-names = "mpu";
+ interrupts = <18>, /* OCP compliant interrupt */
+ <54>, /* TX interrupt */
+ <55>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp4";
+ };
+
+ mcbsp5: mcbsp@48096000 {
+ compatible = "ti,omap2430-mcbsp";
+ reg = <0x48096000 0xff>;
+ reg-names = "mpu";
+ interrupts = <19>, /* OCP compliant interrupt */
+ <81>, /* TX interrupt */
+ <82>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp5";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index cdcb98c7e07..c38cf76df81 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,16 +7,44 @@
*/
/dts-v1/;
-/include/ "omap3.dtsi"
+/include/ "omap36xx.dtsi"
/ {
- model = "TI OMAP3 BeagleBoard";
- compatible = "ti,omap3-beagle", "ti,omap3";
+ model = "TI OMAP3 BeagleBoard xM";
+ compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
+
+ leds {
+ compatible = "gpio-leds";
+ pmu_stat {
+ label = "beagleboard::pmu_stat";
+ gpios = <&twl_gpio 19 0>; /* LEDB */
+ };
+
+ heartbeat {
+ label = "beagleboard::usr0";
+ gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+ linux,default-trigger = "heartbeat";
+ };
+
+ mmc {
+ label = "beagleboard::usr1";
+ gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ sound {
+ compatible = "ti,omap-twl4030";
+ ti,model = "omap3beagle";
+
+ ti,mcbsp = <&mcbsp2>;
+ ti,codec = <&twl_audio>;
+ };
};
&i2c1 {
@@ -27,11 +55,17 @@
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
- vsim: regulator@10 {
+ vsim: regulator-vsim {
compatible = "ti,twl4030-vsim";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
+
+ twl_audio: audio {
+ compatible = "ti,twl4030-audio";
+ codec {
+ };
+ };
};
};
@@ -67,3 +101,15 @@
&mmc3 {
status = "disabled";
};
+
+&twl_gpio {
+ ti,use-leds;
+ /* pullups: BIT(1) */
+ ti,pullups = <0x000002>;
+ /*
+ * pulldowns:
+ * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+ * BIT(15), BIT(16), BIT(17)
+ */
+ ti,pulldowns = <0x03a1c4>;
+};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index f349ee9182c..e8ba1c247a3 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -17,6 +17,15 @@
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
+
+ leds {
+ compatible = "gpio-leds";
+ ledb {
+ label = "omap3evm::ledb";
+ gpios = <&twl_gpio 19 0>; /* LEDB */
+ linux,default-trigger = "default-on";
+ };
+ };
};
&i2c1 {
@@ -46,3 +55,7 @@
reg = <0x5c>;
};
};
+
+&twl_gpio {
+ ti,use-leds;
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
new file mode 100644
index 00000000000..89808ce0167
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * The Gumstix Overo must be combined with an expansion board.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ overo {
+ label = "overo:blue:COM";
+ gpios = <&twl_gpio 19 0>;
+ linux,default-trigger = "mmc0";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <2600000>;
+
+ twl: twl@48 {
+ reg = <0x48>;
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+ };
+};
+
+/include/ "twl4030.dtsi"
+
+/* i2c2 pins are used for gpio */
+&i2c2 {
+ status = "disabled";
+};
+
+/* on board microSD slot */
+&mmc1 {
+ vmmc-supply = <&vmmc1>;
+ bus-width = <4>;
+};
+
+/* optional on board WiFi */
+&mmc2 {
+ bus-width = <4>;
+};
+
+&twl_gpio {
+ ti,use-leds;
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
new file mode 100644
index 00000000000..a13d12de77f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Tobi expansion board is manufactured by Gumstix Inc.
+ */
+
+/include/ "omap3-overo.dtsi"
+
+/ {
+ model = "TI OMAP3 Gumstix Overo on Tobi";
+ compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat {
+ label = "overo:red:gpio21";
+ gpios = <&gpio1 21 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+};
+
+&mmc3 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 81094719820..f38ea8771b4 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -17,7 +17,6 @@
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
- serial3 = &uart4;
};
cpus {
@@ -69,6 +68,24 @@
reg = <0x48200000 0x1000>;
};
+ omap3_pmx_core: pinmux@48002030 {
+ compatible = "ti,omap3-padconf", "pinctrl-single";
+ reg = <0x48002030 0x05cc>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+
+ omap3_pmx_wkup: pinmux@0x48002a58 {
+ compatible = "ti,omap3-padconf", "pinctrl-single";
+ reg = <0x48002a58 0x5c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+
gpio1: gpio@48310000 {
compatible = "ti,omap3-gpio";
ti,hwmods = "gpio1";
@@ -141,12 +158,6 @@
clock-frequency = <48000000>;
};
- uart4: serial@49042000 {
- compatible = "ti,omap3-uart";
- ti,hwmods = "uart4";
- clock-frequency = <48000000>;
- };
-
i2c1: i2c@48070000 {
compatible = "ti,omap3-i2c";
#address-cells = <1>;
@@ -220,5 +231,74 @@
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
};
+
+ mcbsp1: mcbsp@48074000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x48074000 0xff>;
+ reg-names = "mpu";
+ interrupts = <16>, /* OCP compliant interrupt */
+ <59>, /* TX interrupt */
+ <60>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp1";
+ };
+
+ mcbsp2: mcbsp@49022000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x49022000 0xff>,
+ <0x49028000 0xff>;
+ reg-names = "mpu", "sidetone";
+ interrupts = <17>, /* OCP compliant interrupt */
+ <62>, /* TX interrupt */
+ <63>, /* RX interrupt */
+ <4>; /* Sidetone */
+ interrupt-names = "common", "tx", "rx", "sidetone";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <1280>;
+ ti,hwmods = "mcbsp2";
+ };
+
+ mcbsp3: mcbsp@49024000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x49024000 0xff>,
+ <0x4902a000 0xff>;
+ reg-names = "mpu", "sidetone";
+ interrupts = <22>, /* OCP compliant interrupt */
+ <89>, /* TX interrupt */
+ <90>, /* RX interrupt */
+ <5>; /* Sidetone */
+ interrupt-names = "common", "tx", "rx", "sidetone";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp3";
+ };
+
+ mcbsp4: mcbsp@49026000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x49026000 0xff>;
+ reg-names = "mpu";
+ interrupts = <23>, /* OCP compliant interrupt */
+ <54>, /* TX interrupt */
+ <55>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp4";
+ };
+
+ mcbsp5: mcbsp@48096000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x48096000 0xff>;
+ reg-names = "mpu";
+ interrupts = <27>, /* OCP compliant interrupt */
+ <81>, /* TX interrupt */
+ <82>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp5";
+ };
};
};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
new file mode 100644
index 00000000000..96bf0287cb9
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source for OMAP3 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap3.dtsi"
+
+/ {
+ aliases {
+ serial3 = &uart4;
+ };
+
+ ocp {
+ uart4: serial@49042000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9880c12877b..20b966ee1bb 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -8,6 +8,7 @@
/dts-v1/;
/include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
@@ -126,3 +127,13 @@
ti,non-removable;
bus-width = <4>;
};
+
+&emif1 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 72216e932fc..94a23b39033 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -8,6 +8,7 @@
/dts-v1/;
/include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
/ {
model = "TI OMAP4 SDP board";
@@ -18,7 +19,7 @@
reg = <0x80000000 0x40000000>; /* 1 GB */
};
- vdd_eth: fixedregulator@0 {
+ vdd_eth: fixedregulator-vdd-eth {
compatible = "regulator-fixed";
regulator-name = "VDD_ETH";
regulator-min-microvolt = <3300000>;
@@ -28,7 +29,7 @@
regulator-boot-on;
};
- vbat: fixedregulator@2 {
+ vbat: fixedregulator-vbat {
compatible = "regulator-fixed";
regulator-name = "VBAT";
regulator-min-microvolt = <3750000>;
@@ -115,6 +116,33 @@
};
};
+&omap4_pmx_core {
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
+ 0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */
+ 0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
+ 0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ 0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
+ 0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
+ 0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
+ 0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+ >;
+ };
+
+ uart4_pins: pinmux_uart4_pins {
+ pinctrl-single,pins = <
+ 0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */
+ 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */
+ >;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
@@ -226,3 +254,98 @@
bus-width = <4>;
ti,non-removable;
};
+
+&emif1 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+};
+
+&keypad {
+ keypad,num-rows = <8>;
+ keypad,num-columns = <8>;
+ linux,keymap = <0x00000012 /* KEY_E */
+ 0x00010013 /* KEY_R */
+ 0x00020014 /* KEY_T */
+ 0x00030066 /* KEY_HOME */
+ 0x0004003f /* KEY_F5 */
+ 0x000500f0 /* KEY_UNKNOWN */
+ 0x00060017 /* KEY_I */
+ 0x0007002a /* KEY_LEFTSHIFT */
+ 0x01000020 /* KEY_D*/
+ 0x01010021 /* KEY_F */
+ 0x01020022 /* KEY_G */
+ 0x010300e7 /* KEY_SEND */
+ 0x01040040 /* KEY_F6 */
+ 0x010500f0 /* KEY_UNKNOWN */
+ 0x01060025 /* KEY_K */
+ 0x0107001c /* KEY_ENTER */
+ 0x0200002d /* KEY_X */
+ 0x0201002e /* KEY_C */
+ 0x0202002f /* KEY_V */
+ 0x0203006b /* KEY_END */
+ 0x02040041 /* KEY_F7 */
+ 0x020500f0 /* KEY_UNKNOWN */
+ 0x02060034 /* KEY_DOT */
+ 0x0207003a /* KEY_CAPSLOCK */
+ 0x0300002c /* KEY_Z */
+ 0x0301004e /* KEY_KPLUS */
+ 0x03020030 /* KEY_B */
+ 0x0303003b /* KEY_F1 */
+ 0x03040042 /* KEY_F8 */
+ 0x030500f0 /* KEY_UNKNOWN */
+ 0x03060018 /* KEY_O */
+ 0x03070039 /* KEY_SPACE */
+ 0x04000011 /* KEY_W */
+ 0x04010015 /* KEY_Y */
+ 0x04020016 /* KEY_U */
+ 0x0403003c /* KEY_F2 */
+ 0x04040073 /* KEY_VOLUMEUP */
+ 0x040500f0 /* KEY_UNKNOWN */
+ 0x04060026 /* KEY_L */
+ 0x04070069 /* KEY_LEFT */
+ 0x0500001f /* KEY_S */
+ 0x05010023 /* KEY_H */
+ 0x05020024 /* KEY_J */
+ 0x0503003d /* KEY_F3 */
+ 0x05040043 /* KEY_F9 */
+ 0x05050072 /* KEY_VOLUMEDOWN */
+ 0x05060032 /* KEY_M */
+ 0x0507006a /* KEY_RIGHT */
+ 0x06000010 /* KEY_Q */
+ 0x0601001e /* KEY_A */
+ 0x06020031 /* KEY_N */
+ 0x0603009e /* KEY_BACK */
+ 0x0604000e /* KEY_BACKSPACE */
+ 0x060500f0 /* KEY_UNKNOWN */
+ 0x06060019 /* KEY_P */
+ 0x06070067 /* KEY_UP */
+ 0x07000094 /* KEY_PROG1 */
+ 0x07010095 /* KEY_PROG2 */
+ 0x070200ca /* KEY_PROG3 */
+ 0x070300cb /* KEY_PROG4 */
+ 0x0704003e /* KEY_F4 */
+ 0x070500f0 /* KEY_UNKNOWN */
+ 0x07060160 /* KEY_OK */
+ 0x0707006c>; /* KEY_DOWN */
+ linux,input-no-autorepeat;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb6ff9..3883f94fdbd 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -30,12 +30,35 @@
cpus {
cpu@0 {
compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
};
};
+ gic: interrupt-controller@48241000 {
+ compatible = "arm,cortex-a9-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48241000 0x1000>,
+ <0x48240100 0x0100>;
+ };
+
+ L2: l2-cache-controller@48242000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x48242000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ local-timer@0x48240600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x48240600 0x20>;
+ interrupts = <1 13 0x304>;
+ };
+
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
@@ -61,30 +84,6 @@
/*
* XXX: Use a flat representation of the OMAP4 interconnect.
* The real OMAP interconnect network is quite complex.
- *
- * MPU -+-- MPU_PRIVATE - GIC, L2
- * |
- * +----------------+----------+
- * | | |
- * + +- EMIF - DDR |
- * | | |
- * | + +--------+
- * | | |
- * | +- L4_ABE - AESS, MCBSP, TIMERs...
- * | |
- * +- L3_MAIN --+- L4_CORE - IPs...
- * |
- * +- L4_PER - IPs...
- * |
- * +- L4_CFG -+- L4_WKUP - IPs...
- * | |
- * | +- IPs...
- * +- IPU ----+
- * | |
- * +- DSP ----+
- * | |
- * +- DSS ----+
- *
* Since that will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
@@ -96,16 +95,27 @@
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
- gic: interrupt-controller@48241000 {
- compatible = "arm,cortex-a9-gic";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0x48241000 0x1000>,
- <0x48240100 0x0100>;
+ omap4_pmx_core: pinmux@4a100040 {
+ compatible = "ti,omap4-padconf", "pinctrl-single";
+ reg = <0x4a100040 0x0196>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
+ };
+ omap4_pmx_wkup: pinmux@4a31e040 {
+ compatible = "ti,omap4-padconf", "pinctrl-single";
+ reg = <0x4a31e040 0x0038>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0x7fff>;
};
gpio1: gpio@4a310000 {
compatible = "ti,omap4-gpio";
+ reg = <0x4a310000 0x200>;
+ interrupts = <0 29 0x4>;
ti,hwmods = "gpio1";
gpio-controller;
#gpio-cells = <2>;
@@ -115,6 +125,8 @@
gpio2: gpio@48055000 {
compatible = "ti,omap4-gpio";
+ reg = <0x48055000 0x200>;
+ interrupts = <0 30 0x4>;
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
@@ -124,6 +136,8 @@
gpio3: gpio@48057000 {
compatible = "ti,omap4-gpio";
+ reg = <0x48057000 0x200>;
+ interrupts = <0 31 0x4>;
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
@@ -133,6 +147,8 @@
gpio4: gpio@48059000 {
compatible = "ti,omap4-gpio";
+ reg = <0x48059000 0x200>;
+ interrupts = <0 32 0x4>;
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
@@ -142,6 +158,8 @@
gpio5: gpio@4805b000 {
compatible = "ti,omap4-gpio";
+ reg = <0x4805b000 0x200>;
+ interrupts = <0 33 0x4>;
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
@@ -151,6 +169,8 @@
gpio6: gpio@4805d000 {
compatible = "ti,omap4-gpio";
+ reg = <0x4805d000 0x200>;
+ interrupts = <0 34 0x4>;
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
@@ -160,30 +180,40 @@
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
+ reg = <0x4806a000 0x100>;
+ interrupts = <0 72 0x4>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
};
uart2: serial@4806c000 {
compatible = "ti,omap4-uart";
+ reg = <0x4806c000 0x100>;
+ interrupts = <0 73 0x4>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
};
uart3: serial@48020000 {
compatible = "ti,omap4-uart";
+ reg = <0x48020000 0x100>;
+ interrupts = <0 74 0x4>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
};
uart4: serial@4806e000 {
compatible = "ti,omap4-uart";
+ reg = <0x4806e000 0x100>;
+ interrupts = <0 70 0x4>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
};
i2c1: i2c@48070000 {
compatible = "ti,omap4-i2c";
+ reg = <0x48070000 0x100>;
+ interrupts = <0 56 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
@@ -191,6 +221,8 @@
i2c2: i2c@48072000 {
compatible = "ti,omap4-i2c";
+ reg = <0x48072000 0x100>;
+ interrupts = <0 57 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
@@ -198,6 +230,8 @@
i2c3: i2c@48060000 {
compatible = "ti,omap4-i2c";
+ reg = <0x48060000 0x100>;
+ interrupts = <0 61 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
@@ -205,6 +239,8 @@
i2c4: i2c@48350000 {
compatible = "ti,omap4-i2c";
+ reg = <0x48350000 0x100>;
+ interrupts = <0 62 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c4";
@@ -212,6 +248,8 @@
mcspi1: spi@48098000 {
compatible = "ti,omap4-mcspi";
+ reg = <0x48098000 0x200>;
+ interrupts = <0 65 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
@@ -220,6 +258,8 @@
mcspi2: spi@4809a000 {
compatible = "ti,omap4-mcspi";
+ reg = <0x4809a000 0x200>;
+ interrupts = <0 66 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
@@ -228,6 +268,8 @@
mcspi3: spi@480b8000 {
compatible = "ti,omap4-mcspi";
+ reg = <0x480b8000 0x200>;
+ interrupts = <0 91 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
@@ -236,6 +278,8 @@
mcspi4: spi@480ba000 {
compatible = "ti,omap4-mcspi";
+ reg = <0x480ba000 0x200>;
+ interrupts = <0 48 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
@@ -244,6 +288,8 @@
mmc1: mmc@4809c000 {
compatible = "ti,omap4-hsmmc";
+ reg = <0x4809c000 0x400>;
+ interrupts = <0 83 0x4>;
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
@@ -251,30 +297,40 @@
mmc2: mmc@480b4000 {
compatible = "ti,omap4-hsmmc";
+ reg = <0x480b4000 0x400>;
+ interrupts = <0 86 0x4>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
};
mmc3: mmc@480ad000 {
compatible = "ti,omap4-hsmmc";
+ reg = <0x480ad000 0x400>;
+ interrupts = <0 94 0x4>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
};
mmc4: mmc@480d1000 {
compatible = "ti,omap4-hsmmc";
+ reg = <0x480d1000 0x400>;
+ interrupts = <0 96 0x4>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
};
mmc5: mmc@480d5000 {
compatible = "ti,omap4-hsmmc";
+ reg = <0x480d5000 0x400>;
+ interrupts = <0 59 0x4>;
ti,hwmods = "mmc5";
ti,needs-special-reset;
};
wdt2: wdt@4a314000 {
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+ reg = <0x4a314000 0x80>;
+ interrupts = <0 80 0x4>;
ti,hwmods = "wd_timer2";
};
@@ -282,6 +338,7 @@
compatible = "ti,omap4-mcpdm";
reg = <0x40132000 0x7f>, /* MPU private access */
<0x49032000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
interrupts = <0 112 0x4>;
interrupt-parent = <&gic>;
ti,hwmods = "mcpdm";
@@ -291,9 +348,95 @@
compatible = "ti,omap4-dmic";
reg = <0x4012e000 0x7f>, /* MPU private access */
<0x4902e000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
interrupts = <0 114 0x4>;
interrupt-parent = <&gic>;
ti,hwmods = "dmic";
};
+
+ mcbsp1: mcbsp@40122000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x40122000 0xff>, /* MPU private access */
+ <0x49022000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 17 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp1";
+ };
+
+ mcbsp2: mcbsp@40124000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x40124000 0xff>, /* MPU private access */
+ <0x49024000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 22 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp2";
+ };
+
+ mcbsp3: mcbsp@40126000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x40126000 0xff>, /* MPU private access */
+ <0x49026000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 23 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp3";
+ };
+
+ mcbsp4: mcbsp@48096000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x48096000 0xff>; /* L4 Interconnect */
+ reg-names = "mpu";
+ interrupts = <0 16 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp4";
+ };
+
+ keypad: keypad@4a31c000 {
+ compatible = "ti,omap4-keypad";
+ reg = <0x4a31c000 0x80>;
+ interrupts = <0 120 0x4>;
+ reg-names = "mpu";
+ ti,hwmods = "kbd";
+ };
+
+ emif1: emif@4c000000 {
+ compatible = "ti,emif-4d";
+ reg = <0x4c000000 0x100>;
+ interrupts = <0 110 0x4>;
+ ti,hwmods = "emif1";
+ phy-type = <1>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ emif2: emif@4d000000 {
+ compatible = "ti,emif-4d";
+ reg = <0x4d000000 0x100>;
+ interrupts = <0 111 0x4>;
+ ti,hwmods = "emif2";
+ phy-type = <1>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ ocp2scp {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "ocp2scp_usb_phy";
+ };
};
};
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39ad1c8..9c41a3f311a 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,4 +17,68 @@
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
+
+ vmmcsd_fixed: fixedregulator-mmcsd {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <4>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&mmc3 {
+ bus-width = <4>;
+ ti,non-removable;
+};
+
+&mmc4 {
+ status = "disabled";
+};
+
+&mmc5 {
+ status = "disabled";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+
+ /* Pressure Sensor */
+ bmp085@77 {
+ compatible = "bosch,bmp085";
+ reg = <0x77>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+
+ /* Temperature Sensor */
+ tmp102@48{
+ compatible = "ti,tmp102";
+ reg = <0x48>;
+ };
+};
+
+&keypad {
+ keypad,num-rows = <8>;
+ keypad,num-columns = <8>;
+ linux,keymap = <0x02020073 /* VOLUP */
+ 0x02030072 /* VOLDOWM */
+ 0x020400e7 /* SEND */
+ 0x02050066 /* HOME */
+ 0x0206006b /* END */
+ 0x020700d9>; /* SEARCH */
+ linux,input-no-autorepeat;
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e52708374..5db33f481a3 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
cpus {
cpu@0 {
compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /* 14th PPI IRQ, active low level-sensitive */
+ interrupts = <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
};
cpu@1 {
compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /* 14th PPI IRQ, active low level-sensitive */
+ interrupts = <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
};
};
@@ -145,6 +157,41 @@
#interrupt-cells = <1>;
};
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ };
+
+ i2c4: i2c@4807A000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c4";
+ };
+
+ i2c5: i2c@4807C000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c5";
+ };
+
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart1";
@@ -180,5 +227,97 @@
ti,hwmods = "uart6";
clock-frequency = <48000000>;
};
+
+ mmc1: mmc@4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ };
+
+ mmc2: mmc@480b4000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ };
+
+ mmc3: mmc@480ad000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ };
+
+ mmc4: mmc@480d1000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc4";
+ ti,needs-special-reset;
+ };
+
+ mmc5: mmc@480d5000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc5";
+ ti,needs-special-reset;
+ };
+
+ keypad: keypad@4ae1c000 {
+ compatible = "ti,omap4-keypad";
+ ti,hwmods = "kbd";
+ };
+
+ mcpdm: mcpdm@40132000 {
+ compatible = "ti,omap4-mcpdm";
+ reg = <0x40132000 0x7f>, /* MPU private access */
+ <0x49032000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 112 0x4>;
+ interrupt-parent = <&gic>;
+ ti,hwmods = "mcpdm";
+ };
+
+ dmic: dmic@4012e000 {
+ compatible = "ti,omap4-dmic";
+ reg = <0x4012e000 0x7f>, /* MPU private access */
+ <0x4902e000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 114 0x4>;
+ interrupt-parent = <&gic>;
+ ti,hwmods = "dmic";
+ };
+
+ mcbsp1: mcbsp@40122000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x40122000 0xff>, /* MPU private access */
+ <0x49022000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 17 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp1";
+ };
+
+ mcbsp2: mcbsp@40124000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x40124000 0xff>, /* MPU private access */
+ <0x49024000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 22 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp2";
+ };
+
+ mcbsp3: mcbsp@40126000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x40126000 0xff>, /* MPU private access */
+ <0x49026000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 23 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp3";
+ };
};
};
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index 802ec5b2fd0..90fdbd77f27 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -135,13 +135,11 @@
ssp0: ssp@20084000 {
#address-cells = <1>;
#size-cells = <0>;
- pl022,num-chipselects = <1>;
+ num-cs = <1>;
cs-gpios = <&gpio 3 5 0>;
eeprom: at25@0 {
- pl022,hierarchy = <0>;
pl022,interface = <0>;
- pl022,slave-tx-disable = <0>;
pl022,com-mode = <0>;
pl022,rx-level-trig = <1>;
pl022,tx-level-trig = <1>;
@@ -191,16 +189,14 @@
leds {
compatible = "gpio-leds";
- led0 {
- gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
- linux,default-trigger = "heartbeat";
+ led0 { /* red */
+ gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
default-state = "off";
};
- led1 {
- gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
- linux,default-trigger = "timer";
- default-state = "off";
+ led1 { /* green */
+ gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
+ linux,default-trigger = "heartbeat";
};
};
};
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
deleted file mode 100644
index 34ae3a64ba2..00000000000
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ /dev/null
@@ -1,424 +0,0 @@
-/dts-v1/;
-/ {
- model = "SiRF Prima2 eVB";
- compatible = "sirf,prima2-cb", "sirf,prima2";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
-
- memory {
- reg = <0x00000000 0x20000000>;
- };
-
- chosen {
- bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
- linux,stdout-path = &uart1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- reg = <0x0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <32768>;
- i-cache-size = <32768>;
- /* from bootloader */
- timebase-frequency = <0>;
- bus-frequency = <0>;
- clock-frequency = <0>;
- };
- };
-
- axi {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x40000000 0x40000000 0x80000000>;
-
- l2-cache-controller@80040000 {
- compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
- reg = <0x80040000 0x1000>;
- interrupts = <59>;
- arm,tag-latency = <1 1 1>;
- arm,data-latency = <1 1 1>;
- arm,filter-ranges = <0 0x40000000>;
- };
-
- intc: interrupt-controller@80020000 {
- #interrupt-cells = <1>;
- interrupt-controller;
- compatible = "sirf,prima2-intc";
- reg = <0x80020000 0x1000>;
- };
-
- sys-iobg {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x88000000 0x88000000 0x40000>;
-
- clock-controller@88000000 {
- compatible = "sirf,prima2-clkc";
- reg = <0x88000000 0x1000>;
- interrupts = <3>;
- };
-
- reset-controller@88010000 {
- compatible = "sirf,prima2-rstc";
- reg = <0x88010000 0x1000>;
- };
-
- rsc-controller@88020000 {
- compatible = "sirf,prima2-rsc";
- reg = <0x88020000 0x1000>;
- };
- };
-
- mem-iobg {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x90000000 0x90000000 0x10000>;
-
- memory-controller@90000000 {
- compatible = "sirf,prima2-memc";
- reg = <0x90000000 0x10000>;
- interrupts = <27>;
- };
- };
-
- disp-iobg {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x90010000 0x90010000 0x30000>;
-
- display@90010000 {
- compatible = "sirf,prima2-lcd";
- reg = <0x90010000 0x20000>;
- interrupts = <30>;
- };
-
- vpp@90020000 {
- compatible = "sirf,prima2-vpp";
- reg = <0x90020000 0x10000>;
- interrupts = <31>;
- };
- };
-
- graphics-iobg {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x98000000 0x98000000 0x8000000>;
-
- graphics@98000000 {
- compatible = "powervr,sgx531";
- reg = <0x98000000 0x8000000>;
- interrupts = <6>;
- };
- };
-
- multimedia-iobg {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0xa0000000 0xa0000000 0x8000000>;
-
- multimedia@a0000000 {
- compatible = "sirf,prima2-video-codec";
- reg = <0xa0000000 0x8000000>;
- interrupts = <5>;
- };
- };
-
- dsp-iobg {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0xa8000000 0xa8000000 0x2000000>;
-
- dspif@a8000000 {
- compatible = "sirf,prima2-dspif";
- reg = <0xa8000000 0x10000>;
- interrupts = <9>;
- };
-
- gps@a8010000 {
- compatible = "sirf,prima2-gps";
- reg = <0xa8010000 0x10000>;
- interrupts = <7>;
- };
-
- dsp@a9000000 {
- compatible = "sirf,prima2-dsp";
- reg = <0xa9000000 0x1000000>;
- interrupts = <8>;
- };
- };
-
- peri-iobg {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0xb0000000 0xb0000000 0x180000>;
-
- timer@b0020000 {
- compatible = "sirf,prima2-tick";
- reg = <0xb0020000 0x1000>;
- interrupts = <0>;
- };
-
- nand@b0030000 {
- compatible = "sirf,prima2-nand";
- reg = <0xb0030000 0x10000>;
- interrupts = <41>;
- };
-
- audio@b0040000 {
- compatible = "sirf,prima2-audio";
- reg = <0xb0040000 0x10000>;
- interrupts = <35>;
- };
-
- uart0: uart@b0050000 {
- cell-index = <0>;
- compatible = "sirf,prima2-uart";
- reg = <0xb0050000 0x10000>;
- interrupts = <17>;
- };
-
- uart1: uart@b0060000 {
- cell-index = <1>;
- compatible = "sirf,prima2-uart";
- reg = <0xb0060000 0x10000>;
- interrupts = <18>;
- };
-
- uart2: uart@b0070000 {
- cell-index = <2>;
- compatible = "sirf,prima2-uart";
- reg = <0xb0070000 0x10000>;
- interrupts = <19>;
- };
-
- usp0: usp@b0080000 {
- cell-index = <0>;
- compatible = "sirf,prima2-usp";
- reg = <0xb0080000 0x10000>;
- interrupts = <20>;
- };
-
- usp1: usp@b0090000 {
- cell-index = <1>;
- compatible = "sirf,prima2-usp";
- reg = <0xb0090000 0x10000>;
- interrupts = <21>;
- };
-
- usp2: usp@b00a0000 {
- cell-index = <2>;
- compatible = "sirf,prima2-usp";
- reg = <0xb00a0000 0x10000>;
- interrupts = <22>;
- };
-
- dmac0: dma-controller@b00b0000 {
- cell-index = <0>;
- compatible = "sirf,prima2-dmac";
- reg = <0xb00b0000 0x10000>;
- interrupts = <12>;
- };
-
- dmac1: dma-controller@b0160000 {
- cell-index = <1>;
- compatible = "sirf,prima2-dmac";
- reg = <0xb0160000 0x10000>;
- interrupts = <13>;
- };
-
- vip@b00C0000 {
- compatible = "sirf,prima2-vip";
- reg = <0xb00C0000 0x10000>;
- };
-
- spi0: spi@b00d0000 {
- cell-index = <0>;
- compatible = "sirf,prima2-spi";
- reg = <0xb00d0000 0x10000>;
- interrupts = <15>;
- };
-
- spi1: spi@b0170000 {
- cell-index = <1>;
- compatible = "sirf,prima2-spi";
- reg = <0xb0170000 0x10000>;
- interrupts = <16>;
- };
-
- i2c0: i2c@b00e0000 {
- cell-index = <0>;
- compatible = "sirf,prima2-i2c";
- reg = <0xb00e0000 0x10000>;
- interrupts = <24>;
- };
-
- i2c1: i2c@b00f0000 {
- cell-index = <1>;
- compatible = "sirf,prima2-i2c";
- reg = <0xb00f0000 0x10000>;
- interrupts = <25>;
- };
-
- tsc@b0110000 {
- compatible = "sirf,prima2-tsc";
- reg = <0xb0110000 0x10000>;
- interrupts = <33>;
- };
-
- gpio: gpio-controller@b0120000 {
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- compatible = "sirf,prima2-gpio-pinmux";
- reg = <0xb0120000 0x10000>;
- gpio-controller;
- interrupt-controller;
- };
-
- pwm@b0130000 {
- compatible = "sirf,prima2-pwm";
- reg = <0xb0130000 0x10000>;
- };
-
- efusesys@b0140000 {
- compatible = "sirf,prima2-efuse";
- reg = <0xb0140000 0x10000>;
- };
-
- pulsec@b0150000 {
- compatible = "sirf,prima2-pulsec";
- reg = <0xb0150000 0x10000>;
- interrupts = <48>;
- };
-
- pci-iobg {
- compatible = "sirf,prima2-pciiobg", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x56000000 0x56000000 0x1b00000>;
-
- sd0: sdhci@56000000 {
- cell-index = <0>;
- compatible = "sirf,prima2-sdhc";
- reg = <0x56000000 0x100000>;
- interrupts = <38>;
- };
-
- sd1: sdhci@56100000 {
- cell-index = <1>;
- compatible = "sirf,prima2-sdhc";
- reg = <0x56100000 0x100000>;
- interrupts = <38>;
- };
-
- sd2: sdhci@56200000 {
- cell-index = <2>;
- compatible = "sirf,prima2-sdhc";
- reg = <0x56200000 0x100000>;
- interrupts = <23>;
- };
-
- sd3: sdhci@56300000 {
- cell-index = <3>;
- compatible = "sirf,prima2-sdhc";
- reg = <0x56300000 0x100000>;
- interrupts = <23>;
- };
-
- sd4: sdhci@56400000 {
- cell-index = <4>;
- compatible = "sirf,prima2-sdhc";
- reg = <0x56400000 0x100000>;
- interrupts = <39>;
- };
-
- sd5: sdhci@56500000 {
- cell-index = <5>;
- compatible = "sirf,prima2-sdhc";
- reg = <0x56500000 0x100000>;
- interrupts = <39>;
- };
-
- pci-copy@57900000 {
- compatible = "sirf,prima2-pcicp";
- reg = <0x57900000 0x100000>;
- interrupts = <40>;
- };
-
- rom-interface@57a00000 {
- compatible = "sirf,prima2-romif";
- reg = <0x57a00000 0x100000>;
- };
- };
- };
-
- rtc-iobg {
- compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x80030000 0x10000>;
-
- gpsrtc@1000 {
- compatible = "sirf,prima2-gpsrtc";
- reg = <0x1000 0x1000>;
- interrupts = <55 56 57>;
- };
-
- sysrtc@2000 {
- compatible = "sirf,prima2-sysrtc";
- reg = <0x2000 0x1000>;
- interrupts = <52 53 54>;
- };
-
- pwrc@3000 {
- compatible = "sirf,prima2-pwrc";
- reg = <0x3000 0x1000>;
- interrupts = <32>;
- };
- };
-
- uus-iobg {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0xb8000000 0xb8000000 0x40000>;
-
- usb0: usb@b00e0000 {
- compatible = "chipidea,ci13611a-prima2";
- reg = <0xb8000000 0x10000>;
- interrupts = <10>;
- };
-
- usb1: usb@b00f0000 {
- compatible = "chipidea,ci13611a-prima2";
- reg = <0xb8010000 0x10000>;
- interrupts = <11>;
- };
-
- sata@b00f0000 {
- compatible = "synopsys,dwc-ahsata";
- reg = <0xb8020000 0x10000>;
- interrupts = <37>;
- };
-
- security@b00f0000 {
- compatible = "sirf,prima2-security";
- reg = <0xb8030000 0x10000>;
- interrupts = <42>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts
new file mode 100644
index 00000000000..57286b4e7b8
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-evb.dts
@@ -0,0 +1,37 @@
+/*
+ * DTS file for CSR SiRFprimaII Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "prima2.dtsi"
+
+/ {
+ model = "CSR SiRFprimaII Evaluation Board";
+ compatible = "sirf,prima2", "sirf,prima2-cb";
+
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+
+ axi {
+ peri-iobg {
+ uart@b0060000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>;
+ };
+ spi@b00d0000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>;
+ };
+ spi@b0170000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
new file mode 100644
index 00000000000..055fca54212
--- /dev/null
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -0,0 +1,640 @@
+/*
+ * DTS file for CSR SiRFprimaII SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+/ {
+ compatible = "sirf,prima2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
+ /* from bootloader */
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x40000000 0x40000000 0x80000000>;
+
+ l2-cache-controller@80040000 {
+ compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
+ reg = <0x80040000 0x1000>;
+ interrupts = <59>;
+ arm,tag-latency = <1 1 1>;
+ arm,data-latency = <1 1 1>;
+ arm,filter-ranges = <0 0x40000000>;
+ };
+
+ intc: interrupt-controller@80020000 {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "sirf,prima2-intc";
+ reg = <0x80020000 0x1000>;
+ };
+
+ sys-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x88000000 0x88000000 0x40000>;
+
+ clock-controller@88000000 {
+ compatible = "sirf,prima2-clkc";
+ reg = <0x88000000 0x1000>;
+ interrupts = <3>;
+ };
+
+ reset-controller@88010000 {
+ compatible = "sirf,prima2-rstc";
+ reg = <0x88010000 0x1000>;
+ };
+
+ rsc-controller@88020000 {
+ compatible = "sirf,prima2-rsc";
+ reg = <0x88020000 0x1000>;
+ };
+ };
+
+ mem-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x90000000 0x90000000 0x10000>;
+
+ memory-controller@90000000 {
+ compatible = "sirf,prima2-memc";
+ reg = <0x90000000 0x10000>;
+ interrupts = <27>;
+ };
+ };
+
+ disp-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x90010000 0x90010000 0x30000>;
+
+ display@90010000 {
+ compatible = "sirf,prima2-lcd";
+ reg = <0x90010000 0x20000>;
+ interrupts = <30>;
+ };
+
+ vpp@90020000 {
+ compatible = "sirf,prima2-vpp";
+ reg = <0x90020000 0x10000>;
+ interrupts = <31>;
+ };
+ };
+
+ graphics-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x98000000 0x98000000 0x8000000>;
+
+ graphics@98000000 {
+ compatible = "powervr,sgx531";
+ reg = <0x98000000 0x8000000>;
+ interrupts = <6>;
+ };
+ };
+
+ multimedia-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xa0000000 0xa0000000 0x8000000>;
+
+ multimedia@a0000000 {
+ compatible = "sirf,prima2-video-codec";
+ reg = <0xa0000000 0x8000000>;
+ interrupts = <5>;
+ };
+ };
+
+ dsp-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xa8000000 0xa8000000 0x2000000>;
+
+ dspif@a8000000 {
+ compatible = "sirf,prima2-dspif";
+ reg = <0xa8000000 0x10000>;
+ interrupts = <9>;
+ };
+
+ gps@a8010000 {
+ compatible = "sirf,prima2-gps";
+ reg = <0xa8010000 0x10000>;
+ interrupts = <7>;
+ };
+
+ dsp@a9000000 {
+ compatible = "sirf,prima2-dsp";
+ reg = <0xa9000000 0x1000000>;
+ interrupts = <8>;
+ };
+ };
+
+ peri-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xb0000000 0xb0000000 0x180000>;
+
+ timer@b0020000 {
+ compatible = "sirf,prima2-tick";
+ reg = <0xb0020000 0x1000>;
+ interrupts = <0>;
+ };
+
+ nand@b0030000 {
+ compatible = "sirf,prima2-nand";
+ reg = <0xb0030000 0x10000>;
+ interrupts = <41>;
+ };
+
+ audio@b0040000 {
+ compatible = "sirf,prima2-audio";
+ reg = <0xb0040000 0x10000>;
+ interrupts = <35>;
+ };
+
+ uart0: uart@b0050000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-uart";
+ reg = <0xb0050000 0x10000>;
+ interrupts = <17>;
+ };
+
+ uart1: uart@b0060000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-uart";
+ reg = <0xb0060000 0x10000>;
+ interrupts = <18>;
+ };
+
+ uart2: uart@b0070000 {
+ cell-index = <2>;
+ compatible = "sirf,prima2-uart";
+ reg = <0xb0070000 0x10000>;
+ interrupts = <19>;
+ };
+
+ usp0: usp@b0080000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-usp";
+ reg = <0xb0080000 0x10000>;
+ interrupts = <20>;
+ };
+
+ usp1: usp@b0090000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-usp";
+ reg = <0xb0090000 0x10000>;
+ interrupts = <21>;
+ };
+
+ usp2: usp@b00a0000 {
+ cell-index = <2>;
+ compatible = "sirf,prima2-usp";
+ reg = <0xb00a0000 0x10000>;
+ interrupts = <22>;
+ };
+
+ dmac0: dma-controller@b00b0000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-dmac";
+ reg = <0xb00b0000 0x10000>;
+ interrupts = <12>;
+ };
+
+ dmac1: dma-controller@b0160000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-dmac";
+ reg = <0xb0160000 0x10000>;
+ interrupts = <13>;
+ };
+
+ vip@b00C0000 {
+ compatible = "sirf,prima2-vip";
+ reg = <0xb00C0000 0x10000>;
+ };
+
+ spi0: spi@b00d0000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-spi";
+ reg = <0xb00d0000 0x10000>;
+ interrupts = <15>;
+ };
+
+ spi1: spi@b0170000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-spi";
+ reg = <0xb0170000 0x10000>;
+ interrupts = <16>;
+ };
+
+ i2c0: i2c@b00e0000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-i2c";
+ reg = <0xb00e0000 0x10000>;
+ interrupts = <24>;
+ };
+
+ i2c1: i2c@b00f0000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-i2c";
+ reg = <0xb00f0000 0x10000>;
+ interrupts = <25>;
+ };
+
+ tsc@b0110000 {
+ compatible = "sirf,prima2-tsc";
+ reg = <0xb0110000 0x10000>;
+ interrupts = <33>;
+ };
+
+ gpio: pinctrl@b0120000 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "sirf,prima2-pinctrl";
+ reg = <0xb0120000 0x10000>;
+ interrupts = <43 44 45 46 47>;
+ gpio-controller;
+ interrupt-controller;
+
+ lcd_16pins_a: lcd0@0 {
+ lcd {
+ sirf,pins = "lcd_16bitsgrp";
+ sirf,function = "lcd_16bits";
+ };
+ };
+ lcd_18pins_a: lcd0@1 {
+ lcd {
+ sirf,pins = "lcd_18bitsgrp";
+ sirf,function = "lcd_18bits";
+ };
+ };
+ lcd_24pins_a: lcd0@2 {
+ lcd {
+ sirf,pins = "lcd_24bitsgrp";
+ sirf,function = "lcd_24bits";
+ };
+ };
+ lcdrom_pins_a: lcdrom0@0 {
+ lcd {
+ sirf,pins = "lcdromgrp";
+ sirf,function = "lcdrom";
+ };
+ };
+ uart0_pins_a: uart0@0 {
+ uart {
+ sirf,pins = "uart0grp";
+ sirf,function = "uart0";
+ };
+ };
+ uart1_pins_a: uart1@0 {
+ uart {
+ sirf,pins = "uart1grp";
+ sirf,function = "uart1";
+ };
+ };
+ uart2_pins_a: uart2@0 {
+ uart {
+ sirf,pins = "uart2grp";
+ sirf,function = "uart2";
+ };
+ };
+ uart2_noflow_pins_a: uart2@1 {
+ uart {
+ sirf,pins = "uart2_nostreamctrlgrp";
+ sirf,function = "uart2_nostreamctrl";
+ };
+ };
+ spi0_pins_a: spi0@0 {
+ spi {
+ sirf,pins = "spi0grp";
+ sirf,function = "spi0";
+ };
+ };
+ spi1_pins_a: spi1@0 {
+ spi {
+ sirf,pins = "spi1grp";
+ sirf,function = "spi1";
+ };
+ };
+ i2c0_pins_a: i2c0@0 {
+ i2c {
+ sirf,pins = "i2c0grp";
+ sirf,function = "i2c0";
+ };
+ };
+ i2c1_pins_a: i2c1@0 {
+ i2c {
+ sirf,pins = "i2c1grp";
+ sirf,function = "i2c1";
+ };
+ };
+ pwm0_pins_a: pwm0@0 {
+ pwm {
+ sirf,pins = "pwm0grp";
+ sirf,function = "pwm0";
+ };
+ };
+ pwm1_pins_a: pwm1@0 {
+ pwm {
+ sirf,pins = "pwm1grp";
+ sirf,function = "pwm1";
+ };
+ };
+ pwm2_pins_a: pwm2@0 {
+ pwm {
+ sirf,pins = "pwm2grp";
+ sirf,function = "pwm2";
+ };
+ };
+ pwm3_pins_a: pwm3@0 {
+ pwm {
+ sirf,pins = "pwm3grp";
+ sirf,function = "pwm3";
+ };
+ };
+ gps_pins_a: gps@0 {
+ gps {
+ sirf,pins = "gpsgrp";
+ sirf,function = "gps";
+ };
+ };
+ vip_pins_a: vip@0 {
+ vip {
+ sirf,pins = "vipgrp";
+ sirf,function = "vip";
+ };
+ };
+ sdmmc0_pins_a: sdmmc0@0 {
+ sdmmc0 {
+ sirf,pins = "sdmmc0grp";
+ sirf,function = "sdmmc0";
+ };
+ };
+ sdmmc1_pins_a: sdmmc1@0 {
+ sdmmc1 {
+ sirf,pins = "sdmmc1grp";
+ sirf,function = "sdmmc1";
+ };
+ };
+ sdmmc2_pins_a: sdmmc2@0 {
+ sdmmc2 {
+ sirf,pins = "sdmmc2grp";
+ sirf,function = "sdmmc2";
+ };
+ };
+ sdmmc3_pins_a: sdmmc3@0 {
+ sdmmc3 {
+ sirf,pins = "sdmmc3grp";
+ sirf,function = "sdmmc3";
+ };
+ };
+ sdmmc4_pins_a: sdmmc4@0 {
+ sdmmc4 {
+ sirf,pins = "sdmmc4grp";
+ sirf,function = "sdmmc4";
+ };
+ };
+ sdmmc5_pins_a: sdmmc5@0 {
+ sdmmc5 {
+ sirf,pins = "sdmmc5grp";
+ sirf,function = "sdmmc5";
+ };
+ };
+ i2s_pins_a: i2s@0 {
+ i2s {
+ sirf,pins = "i2sgrp";
+ sirf,function = "i2s";
+ };
+ };
+ ac97_pins_a: ac97@0 {
+ ac97 {
+ sirf,pins = "ac97grp";
+ sirf,function = "ac97";
+ };
+ };
+ nand_pins_a: nand@0 {
+ nand {
+ sirf,pins = "nandgrp";
+ sirf,function = "nand";
+ };
+ };
+ usp0_pins_a: usp0@0 {
+ usp0 {
+ sirf,pins = "usp0grp";
+ sirf,function = "usp0";
+ };
+ };
+ usp1_pins_a: usp1@0 {
+ usp1 {
+ sirf,pins = "usp1grp";
+ sirf,function = "usp1";
+ };
+ };
+ usp2_pins_a: usp2@0 {
+ usp2 {
+ sirf,pins = "usp2grp";
+ sirf,function = "usp2";
+ };
+ };
+ usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
+ usb0_utmi_drvbus {
+ sirf,pins = "usb0_utmi_drvbusgrp";
+ sirf,function = "usb0_utmi_drvbus";
+ };
+ };
+ usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
+ usb1_utmi_drvbus {
+ sirf,pins = "usb1_utmi_drvbusgrp";
+ sirf,function = "usb1_utmi_drvbus";
+ };
+ };
+ warm_rst_pins_a: warm_rst@0 {
+ warm_rst {
+ sirf,pins = "warm_rstgrp";
+ sirf,function = "warm_rst";
+ };
+ };
+ pulse_count_pins_a: pulse_count@0 {
+ pulse_count {
+ sirf,pins = "pulse_countgrp";
+ sirf,function = "pulse_count";
+ };
+ };
+ cko0_rst_pins_a: cko0_rst@0 {
+ cko0_rst {
+ sirf,pins = "cko0_rstgrp";
+ sirf,function = "cko0_rst";
+ };
+ };
+ cko1_rst_pins_a: cko1_rst@0 {
+ cko1_rst {
+ sirf,pins = "cko1_rstgrp";
+ sirf,function = "cko1_rst";
+ };
+ };
+ };
+
+ pwm@b0130000 {
+ compatible = "sirf,prima2-pwm";
+ reg = <0xb0130000 0x10000>;
+ };
+
+ efusesys@b0140000 {
+ compatible = "sirf,prima2-efuse";
+ reg = <0xb0140000 0x10000>;
+ };
+
+ pulsec@b0150000 {
+ compatible = "sirf,prima2-pulsec";
+ reg = <0xb0150000 0x10000>;
+ interrupts = <48>;
+ };
+
+ pci-iobg {
+ compatible = "sirf,prima2-pciiobg", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56000000 0x56000000 0x1b00000>;
+
+ sd0: sdhci@56000000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56000000 0x100000>;
+ interrupts = <38>;
+ };
+
+ sd1: sdhci@56100000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56100000 0x100000>;
+ interrupts = <38>;
+ };
+
+ sd2: sdhci@56200000 {
+ cell-index = <2>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56200000 0x100000>;
+ interrupts = <23>;
+ };
+
+ sd3: sdhci@56300000 {
+ cell-index = <3>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56300000 0x100000>;
+ interrupts = <23>;
+ };
+
+ sd4: sdhci@56400000 {
+ cell-index = <4>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56400000 0x100000>;
+ interrupts = <39>;
+ };
+
+ sd5: sdhci@56500000 {
+ cell-index = <5>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56500000 0x100000>;
+ interrupts = <39>;
+ };
+
+ pci-copy@57900000 {
+ compatible = "sirf,prima2-pcicp";
+ reg = <0x57900000 0x100000>;
+ interrupts = <40>;
+ };
+
+ rom-interface@57a00000 {
+ compatible = "sirf,prima2-romif";
+ reg = <0x57a00000 0x100000>;
+ };
+ };
+ };
+
+ rtc-iobg {
+ compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80030000 0x10000>;
+
+ gpsrtc@1000 {
+ compatible = "sirf,prima2-gpsrtc";
+ reg = <0x1000 0x1000>;
+ interrupts = <55 56 57>;
+ };
+
+ sysrtc@2000 {
+ compatible = "sirf,prima2-sysrtc";
+ reg = <0x2000 0x1000>;
+ interrupts = <52 53 54>;
+ };
+
+ pwrc@3000 {
+ compatible = "sirf,prima2-pwrc";
+ reg = <0x3000 0x1000>;
+ interrupts = <32>;
+ };
+ };
+
+ uus-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xb8000000 0xb8000000 0x40000>;
+
+ usb0: usb@b00e0000 {
+ compatible = "chipidea,ci13611a-prima2";
+ reg = <0xb8000000 0x10000>;
+ interrupts = <10>;
+ };
+
+ usb1: usb@b00f0000 {
+ compatible = "chipidea,ci13611a-prima2";
+ reg = <0xb8010000 0x10000>;
+ interrupts = <11>;
+ };
+
+ sata@b00f0000 {
+ compatible = "synopsys,dwc-ahsata";
+ reg = <0xb8020000 0x10000>;
+ interrupts = <37>;
+ };
+
+ security@b00f0000 {
+ compatible = "sirf,prima2-security";
+ reg = <0xb8030000 0x10000>;
+ interrupts = <42>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
new file mode 100644
index 00000000000..d7c5d721a5c
--- /dev/null
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -0,0 +1,14 @@
+/* The pxa3xx skeleton simply augments the 2xx version */
+/include/ "pxa2xx.dtsi"
+
+/ {
+ model = "Marvell PXA27x familiy SoC";
+ compatible = "marvell,pxa27x";
+
+ pxabus {
+ pxairq: interrupt-controller@40d00000 {
+ marvell,intc-priority;
+ marvell,intc-nr-irqs = <34>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
new file mode 100644
index 00000000000..f18aad35e8b
--- /dev/null
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -0,0 +1,132 @@
+/*
+ * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "Marvell PXA2xx family SoC";
+ compatible = "marvell,pxa2xx";
+ interrupt-parent = <&pxairq>;
+
+ aliases {
+ serial0 = &ffuart;
+ serial1 = &btuart;
+ serial2 = &stuart;
+ serial3 = &hwuart;
+ i2c0 = &pwri2c;
+ i2c1 = &pxai2c1;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,xscale";
+ };
+ };
+
+ pxabus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pxairq: interrupt-controller@40d00000 {
+ #interrupt-cells = <1>;
+ compatible = "marvell,pxa-intc";
+ interrupt-controller;
+ interrupt-parent;
+ marvell,intc-nr-irqs = <32>;
+ reg = <0x40d00000 0xd0>;
+ };
+
+ gpio: gpio@40e00000 {
+ compatible = "mrvl,pxa-gpio";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ reg = <0x40e00000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ interrupts = <10>;
+ interrupt-names = "gpio_mux";
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ ranges;
+
+ gcb0: gpio@40e00000 {
+ reg = <0x40e00000 0x4>;
+ };
+
+ gcb1: gpio@40e00004 {
+ reg = <0x40e00004 0x4>;
+ };
+
+ gcb2: gpio@40e00008 {
+ reg = <0x40e00008 0x4>;
+ };
+ gcb3: gpio@40e0000c {
+ reg = <0x40e0000c 0x4>;
+ };
+ };
+
+ ffuart: uart@40100000 {
+ compatible = "mrvl,pxa-uart";
+ reg = <0x40100000 0x30>;
+ interrupts = <22>;
+ status = "disabled";
+ };
+
+ btuart: uart@40200000 {
+ compatible = "mrvl,pxa-uart";
+ reg = <0x40200000 0x30>;
+ interrupts = <21>;
+ status = "disabled";
+ };
+
+ stuart: uart@40700000 {
+ compatible = "mrvl,pxa-uart";
+ reg = <0x40700000 0x30>;
+ interrupts = <20>;
+ status = "disabled";
+ };
+
+ hwuart: uart@41100000 {
+ compatible = "mrvl,pxa-uart";
+ reg = <0x41100000 0x30>;
+ interrupts = <7>;
+ status = "disabled";
+ };
+
+ pxai2c1: i2c@40301680 {
+ compatible = "mrvl,pxa-i2c";
+ reg = <0x40301680 0x30>;
+ interrupts = <18>;
+ #address-cells = <0x1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ usb0: ohci@4c000000 {
+ compatible = "mrvl,pxa-ohci";
+ reg = <0x4c000000 0x10000>;
+ interrupts = <3>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@41100000 {
+ compatible = "mrvl,pxa-mmc";
+ reg = <0x41100000 0x1000>;
+ interrupts = <23>;
+ status = "disabled";
+ };
+
+ rtc@40900000 {
+ compatible = "marvell,pxa-rtc";
+ reg = <0x40900000 0x3c>;
+ interrupts = <30 31>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
new file mode 100644
index 00000000000..f9d92da8678
--- /dev/null
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -0,0 +1,32 @@
+/* The pxa3xx skeleton simply augments the 2xx version */
+/include/ "pxa2xx.dtsi"
+
+/ {
+ model = "Marvell PXA3xx familiy SoC";
+ compatible = "marvell,pxa3xx";
+
+ pxabus {
+ pwri2c: i2c@40f500c0 {
+ compatible = "mrvl,pwri2c";
+ reg = <0x40f500c0 0x30>;
+ interrupts = <6>;
+ #address-cells = <0x1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ nand0: nand@43100000 {
+ compatible = "marvell,pxa3xx-nand";
+ reg = <0x43100000 90>;
+ interrupts = <45>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+
+ pxairq: interrupt-controller@40d00000 {
+ marvell,intc-priority;
+ marvell,intc-nr-irqs = <56>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index e92be5a474e..595492aa505 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -29,6 +29,143 @@
};
twsi1: i2c@d4011000 {
status = "okay";
+
+ pmic: 88pm860x@34 {
+ compatible = "marvell,88pm860x";
+ reg = <0x34>;
+ interrupts = <4>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ marvell,88pm860x-irq-read-clr;
+ marvell,88pm860x-slave-addr = <0x11>;
+
+ regulators {
+ BUCK1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ BUCK2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ BUCK3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ LDO5 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO10 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO12 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ LDO13 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ LDO14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ rtc {
+ marvell,88pm860x-vrtc = <1>;
+ };
+ touch {
+ marvell,88pm860x-gpadc-prebias = <1>;
+ marvell,88pm860x-gpadc-slot-cycle = <1>;
+ marvell,88pm860x-tsi-prebias = <6>;
+ marvell,88pm860x-pen-prebias = <16>;
+ marvell,88pm860x-pen-prechg = <2>;
+ marvell,88pm860x-resistor-X = <300>;
+ };
+ backlights {
+ backlight-0 {
+ marvell,88pm860x-iset = <4>;
+ marvell,88pm860x-pwm = <3>;
+ };
+ backlight-2 {
+ };
+ };
+ leds {
+ led0-red {
+ marvell,88pm860x-iset = <12>;
+ };
+ led0-green {
+ marvell,88pm860x-iset = <12>;
+ };
+ led0-blue {
+ marvell,88pm860x-iset = <12>;
+ };
+ };
+ };
};
rtc: rtc@d4010000 {
status = "okay";
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index aebf32de73b..825aaca3303 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -25,6 +25,11 @@
interrupt-parent = <&intc>;
ranges;
+ L2: l2-cache {
+ compatible = "marvell,tauros2-cache";
+ marvell,tauros2-cache-features = <0x3>;
+ };
+
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
@@ -115,6 +120,8 @@
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
@@ -123,6 +130,8 @@
twsi2: i2c@d4037000 {
compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0xd4037000 0x1000>;
interrupts = <54>;
status = "disabled";
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 7e334d4cae2..702c0baa600 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,7 +10,7 @@
*/
/dts-v1/;
-/include/ "db8500.dtsi"
+/include/ "dbx5x0.dtsi"
/ {
model = "Calao Systems Snowball platform with device tree";
@@ -83,6 +83,22 @@
};
soc-u9500 {
+
+ sound {
+ compatible = "stericsson,snd-soc-mop500";
+
+ stericsson,cpu-dai = <&msp1 &msp3>;
+ stericsson,audio-codec = <&codec>;
+ };
+
+ msp1: msp@80124000 {
+ status = "okay";
+ };
+
+ msp3: msp@80125000 {
+ status = "okay";
+ };
+
external-bus@50000000 {
status = "okay";
@@ -111,7 +127,6 @@
mmc-cap-mmc-highspeed;
vmmc-supply = <&ab8500_ldo_aux3_reg>;
- #gpio-cells = <1>;
cd-gpios = <&gpio6 26 0x4>; // 218
cd-inverted;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index f146dbf6f7f..c3ef1ad26b6 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -275,6 +275,160 @@
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sys_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "sys";
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ reg = <1>;
+ regulator-compatible = "sm0";
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ regulator@2 {
+ reg = <2>;
+ regulator-compatible = "sm1";
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "sm2";
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ regulator@4 {
+ reg = <4>;
+ regulator-compatible = "ldo0";
+ regulator-name = "vdd_ldo0,vddio_pex_clk";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo1";
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo2";
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo3";
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo4";
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo5";
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo6";
+ regulator-name = "vdd_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo7";
+ regulator-name = "vdd_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@12 {
+ reg = <12>;
+ regulator-compatible = "ldo8";
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@13 {
+ reg = <13>;
+ regulator-compatible = "ldo9";
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@14 {
+ reg = <14>;
+ regulator-compatible = "ldo_rtc";
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
};
pmc {
@@ -310,6 +464,72 @@
bus-width = <8>;
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 0>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 0>;
+ enable-active-high;
+ };
+
+ regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "vdd_1v05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&pmic 2 0>;
+ enable-active-high;
+ /* Hack until board-harmony-pcie.c is removed */
+ status = "disabled";
+ };
+
+ regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "vdd_pnl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 22 0>; /* gpio PC6 */
+ enable-active-high;
+ };
+
+ regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 176 0>; /* gpio PW0 */
+ enable-active-high;
+ };
+ };
+
sound {
compatible = "nvidia,tegra-audio-wm8903-harmony",
"nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
new file mode 100644
index 00000000000..a2d6d6541f8
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+ model = "Avionic Design Medcom-Wide board";
+ compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
+
+ i2c@7000c000 {
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <187 0x04>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff
+ 0xffffffff
+ 0
+ 0xffffffff
+ 0xffffffff>;
+ };
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ };
+
+ sound {
+ compatible = "ad,tegra-audio-wm8903-medcom-wide",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Avionic Design Medcom-Wide";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 684a9e1ff7e..ddf287f52d4 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -272,12 +272,170 @@
status = "okay";
clock-frequency = <400000>;
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&p5valw_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sys_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "sys";
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ reg = <1>;
+ regulator-compatible = "sm0";
+ regulator-name = "+1.2vs_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ regulator@2 {
+ reg = <2>;
+ regulator-compatible = "sm1";
+ regulator-name = "+1.0vs_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "sm2";
+ regulator-name = "+3.7vs_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo1";
+ regulator-name = "+1.1vs_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo2";
+ regulator-name = "+1.2vs_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo3";
+ regulator-name = "+3.3vs_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo4";
+ regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo5";
+ regulator-name = "+2.85vs_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo6";
+ /*
+ * Research indicates this should be
+ * 1.8v; other boards that use this
+ * rail for the same purpose need it
+ * set to 1.8v. The schematic signal
+ * name is incorrect; perhaps copied
+ * from an incorrect NVIDIA reference.
+ */
+ regulator-name = "+2.85vs_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo7";
+ regulator-name = "+3.3vs_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@12 {
+ reg = <12>;
+ regulator-compatible = "ldo8";
+ regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@13 {
+ reg = <13>;
+ regulator-compatible = "ldo9";
+ regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@14 {
+ reg = <14>;
+ regulator-compatible = "ldo_rtc";
+ regulator-name = "+3.3vs_rtc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
+ pmc {
+ nvidia,invert-interrupt;
+ };
+
usb@c5000000 {
status = "okay";
};
@@ -325,6 +483,21 @@
};
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ p5valw_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "+5valw";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+ };
+
sound {
compatible = "nvidia,tegra-audio-alc5632-paz00",
"nvidia,tegra-audio-alc5632";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
new file mode 100644
index 00000000000..331a3ef24d5
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -0,0 +1,50 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+ model = "Avionic Design Plutux board";
+ compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
+
+ i2c@7000c000 {
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <187 0x04>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff
+ 0xffffffff
+ 0
+ 0xffffffff
+ 0xffffffff>;
+ };
+ };
+
+ sound {
+ compatible = "ad,tegra-audio-plutux",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Avionic Design Plutux";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 85e621ab296..e60dc7124e9 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -374,6 +374,154 @@
status = "okay";
clock-frequency = <400000>;
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sys_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "sys";
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ reg = <1>;
+ regulator-compatible = "sm0";
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ };
+
+ regulator@2 {
+ reg = <2>;
+ regulator-compatible = "sm1";
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <1125000>;
+ regulator-max-microvolt = <1125000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "sm2";
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo1";
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo2";
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo3";
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo4";
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo5";
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo6";
+ regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo7";
+ regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@12 {
+ reg = <12>;
+ regulator-compatible = "ldo8";
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@13 {
+ reg = <13>;
+ regulator-compatible = "ldo9";
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@14 {
+ reg = <14>;
+ regulator-compatible = "ldo_rtc";
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
temperature-sensor@4c {
compatible = "nct1008";
reg = <0x4c>;
@@ -387,6 +535,10 @@
};
};
+ pmc {
+ nvidia,invert-interrupt;
+ };
+
memory-controller@0x7000f400 {
emc-table@190000 {
reg = <190000>;
@@ -473,6 +625,40 @@
};
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 0>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 0>;
+ enable-active-high;
+ };
+ };
+
sound {
compatible = "nvidia,tegra-audio-wm8903-seaboard",
"nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
new file mode 100644
index 00000000000..f18cec9f6a7
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -0,0 +1,449 @@
+/include/ "tegra20.dtsi"
+
+/ {
+ model = "Avionic Design Tamonten SOM";
+ compatible = "ad,tamonten", "nvidia,tegra20";
+
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ atc {
+ nvidia,pins = "atc";
+ nvidia,function = "nand";
+ };
+ atd {
+ nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+ "spia", "spib", "spic";
+ nvidia,function = "gmi";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ dta {
+ nvidia,pins = "dta", "dtd";
+ nvidia,function = "sdio2";
+ };
+ dtb {
+ nvidia,pins = "dtb", "dtc", "dte";
+ nvidia,function = "rsvd1";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gmc {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa", "slxk";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint", "pta";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uarta";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+ "lhs", "lm0", "lm1", "lpp", "lpw0",
+ "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+ "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "spdi", "spdo", "uac";
+ nvidia,function = "rsvd2";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd";
+ nvidia,function = "pwm";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxc {
+ nvidia,pins = "slxc", "slxd";
+ nvidia,function = "spdif";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+ "cdev1", "cdev2", "dap1", "dtb", "gma",
+ "gmb", "gmc", "gmd", "gme", "gpu7",
+ "gpv", "i2cp", "pta", "rm", "slxa",
+ "slxk", "spia", "spib", "uac";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <0>;
+ };
+ conf_csus {
+ nvidia,pins = "csus", "spid", "spif";
+ nvidia,pull = <1>;
+ nvidia,tristate = <1>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+ "dtc", "dte", "dtf", "gpu", "sdio1",
+ "slxc", "slxd", "spdi", "spdo", "spig",
+ "uda";
+ nvidia,pull = <0>;
+ nvidia,tristate = <1>;
+ };
+ conf_ddc {
+ nvidia,pins = "ddc", "dta", "dtd", "kbca",
+ "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+ "sdc";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+ "lvp0", "owc", "sdb";
+ nvidia,tristate = <1>;
+ };
+ conf_irrx {
+ nvidia,pins = "irrx", "irtx", "sdd", "spic",
+ "spie", "spih", "uaa", "uab", "uad",
+ "uca", "ucb";
+ nvidia,pull = <2>;
+ nvidia,tristate = <1>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <2>;
+ };
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+ "lvs", "pmc";
+ nvidia,tristate = <0>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <1>;
+ };
+ };
+ };
+
+ i2s@70002800 {
+ status = "okay";
+ };
+
+ serial@70006300 {
+ clock-frequency = <216000000>;
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ clock-frequency = <400000>;
+ status = "okay";
+ };
+
+ i2c@7000d000 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sys_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "sys";
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ reg = <1>;
+ regulator-compatible = "sm0";
+ regulator-name = "vdd_sys_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ regulator@2 {
+ reg = <2>;
+ regulator-compatible = "sm1";
+ regulator-name = "vdd_sys_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "sm2";
+ regulator-name = "vdd_sys_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ regulator@4 {
+ reg = <4>;
+ regulator-compatible = "ldo0";
+ regulator-name = "vdd_ldo0,vddio_pex_clk";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo1";
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo2";
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo3";
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo4";
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo5";
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo6";
+ regulator-name = "vdd_ldo6,avdd_vdac";
+ /*
+ * According to the Tegra 2 Automotive
+ * DataSheet, a typical value for this
+ * would be 2.8V, but the PMIC only
+ * supports 2.85V.
+ */
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo7";
+ regulator-name = "vdd_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@12 {
+ reg = <12>;
+ regulator-compatible = "ldo8";
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@13 {
+ reg = <13>;
+ regulator-compatible = "ldo9";
+ regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
+ /*
+ * According to the Tegra 2 Automotive
+ * DataSheet, a typical value for this
+ * would be 2.8V, but the PMIC only
+ * supports 2.85V.
+ */
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@14 {
+ reg = <14>;
+ regulator-compatible = "ldo_rtc";
+ regulator-name = "vdd_rtc_out";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ sdhci@c8000600 {
+ cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+ wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+ bus-width = <4>;
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
new file mode 100644
index 00000000000..9aff31b0fe4
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -0,0 +1,53 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+ model = "Avionic Design Tamonten Evaluation Carrier";
+ compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
+
+ i2c@7000c000 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <187 0x04>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff
+ 0xffffffff
+ 0
+ 0xffffffff
+ 0xffffffff>;
+ };
+ };
+
+ sound {
+ compatible = "ad,tegra-audio-wm8903-tec",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Avionic Design TEC";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index be90544e6b5..3e5952fcfbc 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -289,6 +289,158 @@
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sys_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "sys";
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ reg = <1>;
+ regulator-compatible = "sm0";
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ regulator@2 {
+ reg = <2>;
+ regulator-compatible = "sm1";
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "sm2";
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo1";
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo2";
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo3";
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo4";
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo5";
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo6";
+ regulator-name = "vdd_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo7";
+ regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@12 {
+ reg = <12>;
+ regulator-compatible = "ldo8";
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@13 {
+ reg = <13>;
+ regulator-compatible = "ldo9";
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@14 {
+ reg = <14>;
+ regulator-compatible = "ldo_rtc";
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
};
usb@c5000000 {
@@ -317,6 +469,60 @@
bus-width = <8>;
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 0>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 0>;
+ enable-active-high;
+ };
+
+ regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "vdd_pnl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 22 0>; /* gpio PC6 */
+ enable-active-high;
+ };
+
+ regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 176 0>; /* gpio PW0 */
+ enable-active-high;
+ };
+ };
+
sound {
compatible = "nvidia,tegra-audio-wm8903-ventana",
"nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 6916310bf58..c636d002d6d 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -261,6 +261,286 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ max8907@3c {
+ compatible = "maxim,max8907";
+ reg = <0x3c>;
+ interrupts = <0 86 0x4>;
+
+ maxim,system-power-controller;
+
+ mbatt-supply = <&usb0_vbus_reg>;
+ in-v1-supply = <&mbatt_reg>;
+ in-v2-supply = <&mbatt_reg>;
+ in-v3-supply = <&mbatt_reg>;
+ in1-supply = <&mbatt_reg>;
+ in2-supply = <&nvvdd_sv3_reg>;
+ in3-supply = <&mbatt_reg>;
+ in4-supply = <&mbatt_reg>;
+ in5-supply = <&mbatt_reg>;
+ in6-supply = <&mbatt_reg>;
+ in7-supply = <&mbatt_reg>;
+ in8-supply = <&mbatt_reg>;
+ in9-supply = <&mbatt_reg>;
+ in10-supply = <&mbatt_reg>;
+ in11-supply = <&mbatt_reg>;
+ in12-supply = <&mbatt_reg>;
+ in13-supply = <&mbatt_reg>;
+ in14-supply = <&mbatt_reg>;
+ in15-supply = <&mbatt_reg>;
+ in16-supply = <&mbatt_reg>;
+ in17-supply = <&nvvdd_sv3_reg>;
+ in18-supply = <&nvvdd_sv3_reg>;
+ in19-supply = <&mbatt_reg>;
+ in20-supply = <&mbatt_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mbatt_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "mbatt";
+ regulator-name = "vbat_pmu";
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ reg = <1>;
+ regulator-compatible = "sd1";
+ regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ regulator@2 {
+ reg = <2>;
+ regulator-compatible = "sd2";
+ regulator-name = "nvvdd_sv2,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ nvvdd_sv3_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "sd3";
+ regulator-name = "nvvdd_sv3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ regulator@4 {
+ reg = <4>;
+ regulator-compatible = "ldo1";
+ regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo2";
+ regulator-name = "nvvdd_ldo2,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo3";
+ regulator-name = "nvvdd_ldo3,vcom_1v8b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo4";
+ regulator-name = "nvvdd_ldo4,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo5";
+ regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo6";
+ regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo7";
+ regulator-name = "nvvdd_ldo7,avddio_audio";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo8";
+ regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ regulator@12 {
+ reg = <12>;
+ regulator-compatible = "ldo9";
+ regulator-name = "nvvdd_ldo9,avdd_cam*";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ regulator@13 {
+ reg = <13>;
+ regulator-compatible = "ldo10";
+ regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ regulator@14 {
+ reg = <14>;
+ regulator-compatible = "ldo11";
+ regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@15 {
+ reg = <15>;
+ regulator-compatible = "ldo12";
+ regulator-name = "nvvdd_ldo12,vddio_sdio";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ regulator@16 {
+ reg = <16>;
+ regulator-compatible = "ldo13";
+ regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ regulator@17 {
+ reg = <17>;
+ regulator-compatible = "ldo14";
+ regulator-name = "nvvdd_ldo14,avdd_vdac";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ regulator@18 {
+ reg = <18>;
+ regulator-compatible = "ldo15";
+ regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@19 {
+ reg = <19>;
+ regulator-compatible = "ldo16";
+ regulator-name = "nvvdd_ldo16,vdd_dbrtr";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ regulator@20 {
+ reg = <20>;
+ regulator-compatible = "ldo17";
+ regulator-name = "nvvdd_ldo17,vddio_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ regulator@21 {
+ reg = <21>;
+ regulator-compatible = "ldo18";
+ regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@22 {
+ reg = <22>;
+ regulator-compatible = "ldo19";
+ regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ regulator@23 {
+ reg = <23>;
+ regulator-compatible = "ldo20";
+ regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ regulator@24 {
+ reg = <24>;
+ regulator-compatible = "out5v";
+ regulator-name = "usb0_vbus_reg";
+ };
+
+ regulator@25 {
+ reg = <25>;
+ regulator-compatible = "out33v";
+ regulator-name = "pmu_out3v3";
+ };
+
+ regulator@26 {
+ reg = <26>;
+ regulator-compatible = "bbat";
+ regulator-name = "pmu_bbat";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <2400000>;
+ regulator-always-on;
+ };
+
+ regulator@27 {
+ reg = <27>;
+ regulator-compatible = "sdby";
+ regulator-name = "vdd_aon";
+ regulator-always-on;
+ };
+
+ regulator@28 {
+ reg = <28>;
+ regulator-compatible = "vrtc";
+ regulator-name = "vrtc,pmu_vccadc";
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ pmc {
+ nvidia,invert-interrupt;
};
usb@c5000000 {
@@ -284,6 +564,21 @@
bus-width = <8>;
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb0_vbus_reg: regulator {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+ };
+
sound {
compatible = "nvidia,tegra-audio-wm8753-whistler",
"nvidia,tegra-audio-wm8753";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 405d1673904..67a6cd910b9 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -123,7 +123,7 @@
status = "disabled";
};
- pwm {
+ pwm: pwm {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
new file mode 100644
index 00000000000..dd4222f00ec
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -0,0 +1,87 @@
+/dts-v1/;
+
+/include/ "tegra30-cardhu.dtsi"
+
+/* This dts file support the cardhu A02 version of board */
+
+/ {
+ model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
+ compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ddr_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ reg = <100>;
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 0>;
+ };
+
+ sys_3v3_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ reg = <101>;
+ regulator-name = "sys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 0>;
+ };
+
+ usb1_vbus_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ reg = <102>;
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 68 0>; /* GPIO PI4 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ usb3_vbus_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ reg = <103>;
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 63 0>; /* GPIO PH7 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ vdd_5v0_reg: regulator@104 {
+ compatible = "regulator-fixed";
+ reg = <104>;
+ regulator-name = "5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pmic 2 0>;
+ };
+
+ vdd_bl_reg: regulator@105 {
+ compatible = "regulator-fixed";
+ reg = <105>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 83 0>; /* GPIO PK3 */
+ };
+ };
+};
+
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
new file mode 100644
index 00000000000..0828f097ca8
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -0,0 +1,98 @@
+/dts-v1/;
+
+/include/ "tegra30-cardhu.dtsi"
+
+/* This dts file support the cardhu A04 and later versions of board */
+
+/ {
+ model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
+ compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ddr_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "ddr";
+ reg = <100>;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 0>;
+ };
+
+ sys_3v3_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ reg = <101>;
+ regulator-name = "sys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 0>;
+ };
+
+ usb1_vbus_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ reg = <102>;
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 238 0>; /* GPIO PDD6 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ usb3_vbus_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ reg = <103>;
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 236 0>; /* GPIO PDD4 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ vdd_5v0_reg: regulator@104 {
+ compatible = "regulator-fixed";
+ reg = <104>;
+ regulator-name = "5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pmic 8 0>;
+ };
+
+ vdd_bl_reg: regulator@105 {
+ compatible = "regulator-fixed";
+ reg = <105>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 234 0>; /* GPIO PDD2 */
+ };
+
+ vdd_bl2_reg: regulator@106 {
+ compatible = "regulator-fixed";
+ reg = <106>;
+ regulator-name = "vdd_bl2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 232 0>; /* GPIO PDD0 */
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts
deleted file mode 100644
index c169bced131..00000000000
--- a/arch/arm/boot/dts/tegra30-cardhu.dts
+++ /dev/null
@@ -1,171 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra30.dtsi"
-
-/ {
- model = "NVIDIA Tegra30 Cardhu evaluation board";
- compatible = "nvidia,cardhu", "nvidia,tegra30";
-
- memory {
- reg = <0x80000000 0x40000000>;
- };
-
- pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- sdmmc1_clk_pz0 {
- nvidia,pins = "sdmmc1_clk_pz0";
- nvidia,function = "sdmmc1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc1_cmd_pz1 {
- nvidia,pins = "sdmmc1_cmd_pz1",
- "sdmmc1_dat0_py7",
- "sdmmc1_dat1_py6",
- "sdmmc1_dat2_py5",
- "sdmmc1_dat3_py4";
- nvidia,function = "sdmmc1";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- sdmmc4_clk_pcc4 {
- nvidia,pins = "sdmmc4_clk_pcc4",
- "sdmmc4_rst_n_pcc3";
- nvidia,function = "sdmmc4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc4_dat0_paa0 {
- nvidia,pins = "sdmmc4_dat0_paa0",
- "sdmmc4_dat1_paa1",
- "sdmmc4_dat2_paa2",
- "sdmmc4_dat3_paa3",
- "sdmmc4_dat4_paa4",
- "sdmmc4_dat5_paa5",
- "sdmmc4_dat6_paa6",
- "sdmmc4_dat7_paa7";
- nvidia,function = "sdmmc4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- dap2_fs_pa2 {
- nvidia,pins = "dap2_fs_pa2",
- "dap2_sclk_pa3",
- "dap2_din_pa4",
- "dap2_dout_pa5";
- nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- };
- };
-
- serial@70006000 {
- status = "okay";
- clock-frequency = <408000000>;
- };
-
- i2c@7000c000 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000c500 {
- status = "okay";
- clock-frequency = <100000>;
-
- /* ALS and Proximity sensor */
- isl29028@44 {
- compatible = "isil,isl29028";
- reg = <0x44>;
- interrupt-parent = <&gpio>;
- interrupts = <88 0x04>; /*gpio PL0 */
- };
- };
-
- i2c@7000c700 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <100000>;
-
- wm8903: wm8903@1a {
- compatible = "wlf,wm8903";
- reg = <0x1a>;
- interrupt-parent = <&gpio>;
- interrupts = <179 0x04>; /* gpio PW3 */
-
- gpio-controller;
- #gpio-cells = <2>;
-
- micdet-cfg = <0>;
- micdet-delay = <100>;
- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
- };
-
- tps62361 {
- compatible = "ti,tps62361";
- reg = <0x60>;
-
- regulator-name = "tps62361-vout";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- regulator-always-on;
- ti,vsel0-state-high;
- ti,vsel1-state-high;
- };
- };
-
- ahub {
- i2s@70080400 {
- status = "okay";
- };
- };
-
- sdhci@78000000 {
- status = "okay";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 155 0>; /* gpio PT3 */
- power-gpios = <&gpio 31 0>; /* gpio PD7 */
- bus-width = <4>;
- };
-
- sdhci@78000600 {
- status = "okay";
- bus-width = <8>;
- };
-
- sound {
- compatible = "nvidia,tegra-audio-wm8903-cardhu",
- "nvidia,tegra-audio-wm8903";
- nvidia,model = "NVIDIA Tegra Cardhu";
-
- nvidia,audio-routing =
- "Headphone Jack", "HPOUTR",
- "Headphone Jack", "HPOUTL",
- "Int Spk", "ROP",
- "Int Spk", "RON",
- "Int Spk", "LOP",
- "Int Spk", "LON",
- "Mic Jack", "MICBIAS",
- "IN1L", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&wm8903>;
-
- nvidia,spkr-en-gpios = <&wm8903 2 0>;
- nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
- };
-};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
new file mode 100644
index 00000000000..d10c9c5a360
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -0,0 +1,475 @@
+/include/ "tegra30.dtsi"
+
+/**
+ * This file contains common DT entry for all fab version of Cardhu.
+ * There is multiple fab version of Cardhu starting from A01 to A07.
+ * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
+ * A02 will have different sets of GPIOs for fixed regulator compare to
+ * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
+ * compatible with fab version A04. Based on Cardhu fab version, the
+ * related dts file need to be chosen like for Cardhu fab version A02,
+ * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
+ * tegra30-cardhu-a04.dts.
+ * The identification of board is done in two ways, by looking the sticker
+ * on PCB and by reading board id eeprom.
+ * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
+ * number is the fab version like here it is 002 and hence fab version A02.
+ * The (downstream internal) U-Boot of Cardhu display the board-id as
+ * follows:
+ * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
+ * In this Fab version is 02 i.e. A02.
+ * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
+ * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
+ * wide.
+ */
+
+/ {
+ model = "NVIDIA Tegra30 Cardhu evaluation board";
+ compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc1_cmd_pz1 {
+ nvidia,pins = "sdmmc1_cmd_pz1",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4",
+ "sdmmc4_rst_n_pcc3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ };
+ };
+
+ serial@70006000 {
+ status = "okay";
+ clock-frequency = <408000000>;
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ /* ALS and Proximity sensor */
+ isl29028@44 {
+ compatible = "isil,isl29028";
+ reg = <0x44>;
+ interrupt-parent = <&gpio>;
+ interrupts = <88 0x04>; /*gpio PL0 */
+ };
+ };
+
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ wm8903: wm8903@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <179 0x04>; /* gpio PW3 */
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+ };
+
+ tps62361 {
+ compatible = "ti,tps62361";
+ reg = <0x60>;
+
+ regulator-name = "tps62361-vout";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ };
+
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <0 86 0x4>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ vcc1-supply = <&vdd_ac_bat_reg>;
+ vcc2-supply = <&vdd_ac_bat_reg>;
+ vcc3-supply = <&vio_reg>;
+ vcc4-supply = <&vdd_5v0_reg>;
+ vcc5-supply = <&vdd_ac_bat_reg>;
+ vcc6-supply = <&vdd2_reg>;
+ vcc7-supply = <&vdd_ac_bat_reg>;
+ vccio-supply = <&vdd_ac_bat_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd1_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "vdd1";
+ regulator-name = "vddio_ddr_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "vdd2";
+ regulator-name = "vdd_1v5_gen";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vddctrl_reg: regulator@2 {
+ reg = <2>;
+ regulator-compatible = "vddctrl";
+ regulator-name = "vdd_cpu,vdd_sys";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "vio";
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "ldo1";
+ regulator-name = "vdd_pexa,vdd_pexb";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ ldo2_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo2";
+ regulator-name = "vdd_sata,avdd_plle";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ /* LDO3 is not connected to anything */
+
+ ldo4_reg: regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo4";
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo5";
+ regulator-name = "vddio_sdmmc,avdd_vdac";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo6";
+ regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo7_reg: regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo7";
+ regulator-name = "vdd_pllm,x,u,a_p_c_s";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo8";
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ ahub {
+ i2s@70080400 {
+ status = "okay";
+ };
+ };
+
+ pmc {
+ status = "okay";
+ nvidia,invert-interrupt;
+ };
+
+ sdhci@78000000 {
+ status = "okay";
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+ power-gpios = <&gpio 31 0>; /* gpio PD7 */
+ bus-width = <4>;
+ };
+
+ sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_ac_bat_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_ac_bat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ cam_1v8_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "cam_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ gpio = <&gpio 220 0>; /* gpio PBB4 */
+ vin-supply = <&vio_reg>;
+ };
+
+ cp_5v_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "cp_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+ };
+
+ emmc_3v3_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "emmc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 25 0>; /* gpio PD1 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ modem_3v3_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "modem_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio 30 0>; /* gpio PD6 */
+ };
+
+ pex_hvdd_3v3_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "pex_hvdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio 95 0>; /* gpio PL7 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_cam1_ldo_reg: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "vdd_cam1_ldo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&gpio 142 0>; /* gpio PR6 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_cam2_ldo_reg: regulator@7 {
+ compatible = "regulator-fixed";
+ reg = <7>;
+ regulator-name = "vdd_cam2_ldo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&gpio 143 0>; /* gpio PR7 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_cam3_ldo_reg: regulator@8 {
+ compatible = "regulator-fixed";
+ reg = <8>;
+ regulator-name = "vdd_cam3_ldo";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio 144 0>; /* gpio PS0 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_com_reg: regulator@9 {
+ compatible = "regulator-fixed";
+ reg = <9>;
+ regulator-name = "vdd_com";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio 24 0>; /* gpio PD0 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_fuse_3v3_reg: regulator@10 {
+ compatible = "regulator-fixed";
+ reg = <10>;
+ regulator-name = "vdd_fuse_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio 94 0>; /* gpio PL6 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_pnl1_reg: regulator@11 {
+ compatible = "regulator-fixed";
+ reg = <11>;
+ regulator-name = "vdd_pnl1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio 92 0>; /* gpio PL4 */
+ vin-supply = <&sys_3v3_reg>;
+ };
+
+ vdd_vid_reg: regulator@12 {
+ compatible = "regulator-fixed";
+ reg = <12>;
+ regulator-name = "vddio_vid";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio 152 0>; /* GPIO PT0 */
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-wm8903-cardhu",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "NVIDIA Tegra Cardhu";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 0>;
+ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 3e4334d14ef..b1497c7d7d6 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -117,7 +117,7 @@
status = "disabled";
};
- pwm {
+ pwm: pwm {
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
new file mode 100644
index 00000000000..a63272422d7
--- /dev/null
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+
+&tps {
+ compatible = "ti,tps65217";
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dcdc1_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "dcdc1";
+ };
+
+ dcdc2_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "dcdc2";
+ };
+
+ dcdc3_reg: regulator@2 {
+ reg = <2>;
+ regulator-compatible = "dcdc3";
+ };
+
+ ldo1_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "ldo1";
+ };
+
+ ldo2_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "ldo2";
+ };
+
+ ldo3_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo3";
+ };
+
+ ldo4_reg: regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo4";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
new file mode 100644
index 00000000000..92693a89160
--- /dev/null
+++ b/arch/arm/boot/dts/tps65910.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65910.pdf
+ */
+
+&tps {
+ compatible = "ti,tps65910";
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vrtc_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "vrtc";
+ };
+
+ vio_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "vio";
+ };
+
+ vdd1_reg: regulator@2 {
+ reg = <2>;
+ regulator-compatible = "vdd1";
+ };
+
+ vdd2_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "vdd2";
+ };
+
+ vdd3_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "vdd3";
+ };
+
+ vdig1_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "vdig1";
+ };
+
+ vdig2_reg: regulator@6 {
+ reg = <6>;
+ regulator-compatible = "vdig2";
+ };
+
+ vpll_reg: regulator@7 {
+ reg = <7>;
+ regulator-compatible = "vpll";
+ };
+
+ vdac_reg: regulator@8 {
+ reg = <8>;
+ regulator-compatible = "vdac";
+ };
+
+ vaux1_reg: regulator@9 {
+ reg = <9>;
+ regulator-compatible = "vaux1";
+ };
+
+ vaux2_reg: regulator@10 {
+ reg = <10>;
+ regulator-compatible = "vaux2";
+ };
+
+ vaux33_reg: regulator@11 {
+ reg = <11>;
+ regulator-compatible = "vaux33";
+ };
+
+ vmmc_reg: regulator@12 {
+ reg = <12>;
+ regulator-compatible = "vmmc";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 22f4d1394ed..ff000172c93 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -19,19 +19,19 @@
interrupts = <11>;
};
- vdac: regulator@0 {
+ vdac: regulator-vdac {
compatible = "ti,twl4030-vdac";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vpll2: regulator@1 {
+ vpll2: regulator-vpll2 {
compatible = "ti,twl4030-vpll2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vmmc1: regulator@2 {
+ vmmc1: regulator-vmmc1 {
compatible = "ti,twl4030-vmmc1";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <3150000>;
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 3b2f3510d7e..123e2c40218 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -20,67 +20,70 @@
interrupts = <11>;
};
- vaux1: regulator@0 {
+ vaux1: regulator-vaux1 {
compatible = "ti,twl6030-vaux1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
};
- vaux2: regulator@1 {
+ vaux2: regulator-vaux2 {
compatible = "ti,twl6030-vaux2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2800000>;
};
- vaux3: regulator@2 {
+ vaux3: regulator-vaux3 {
compatible = "ti,twl6030-vaux3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
};
- vmmc: regulator@3 {
+ vmmc: regulator-vmmc {
compatible = "ti,twl6030-vmmc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
};
- vpp: regulator@4 {
+ vpp: regulator-vpp {
compatible = "ti,twl6030-vpp";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2500000>;
};
- vusim: regulator@5 {
+ vusim: regulator-vusim {
compatible = "ti,twl6030-vusim";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2900000>;
};
- vdac: regulator@6 {
+ vdac: regulator-vdac {
compatible = "ti,twl6030-vdac";
};
- vana: regulator@7 {
+ vana: regulator-vana {
compatible = "ti,twl6030-vana";
};
- vcxio: regulator@8 {
+ vcxio: regulator-vcxio {
compatible = "ti,twl6030-vcxio";
+ regulator-always-on;
};
- vusb: regulator@9 {
+ vusb: regulator-vusb {
compatible = "ti,twl6030-vusb";
};
- v1v8: regulator@10 {
+ v1v8: regulator-v1v8 {
compatible = "ti,twl6030-v1v8";
+ regulator-always-on;
};
- v2v1: regulator@11 {
+ v2v1: regulator-v2v1 {
compatible = "ti,twl6030-v2v1";
+ regulator-always-on;
};
- clk32kg: regulator@12 {
+ clk32kg: regulator-clk32kg {
compatible = "ti,twl6030-clk32kg";
};
};
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
new file mode 100644
index 00000000000..567cf4e8ab8
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -0,0 +1,36 @@
+/*
+ * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "vt8500.dtsi"
+
+/ {
+ model = "Benign BV07 Netbook";
+
+ /*
+ * Display node is based on Sascha Hauer's patch on dri-devel.
+ * Added a bpp property to calculate the size of the framebuffer
+ * until the binding is formalized.
+ */
+ display: display@0 {
+ modes {
+ mode0: mode@0 {
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <88>;
+ hfront-porch = <40>;
+ hsync-len = <0>;
+ vback-porch = <32>;
+ vfront-porch = <11>;
+ vsync-len = <1>;
+ clock = <0>; /* unused but required */
+ bpp = <16>; /* non-standard but required */
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
new file mode 100644
index 00000000000..d8645e990b2
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -0,0 +1,116 @@
+/*
+ * vt8500.dtsi - Device tree file for VIA VT8500 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "via,vt8500";
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&intc>;
+
+ intc: interrupt-controller@d8140000 {
+ compatible = "via,vt8500-intc";
+ interrupt-controller;
+ reg = <0xd8140000 0x10000>;
+ #interrupt-cells = <1>;
+ };
+
+ gpio: gpio-controller@d8110000 {
+ compatible = "via,vt8500-gpio";
+ gpio-controller;
+ reg = <0xd8110000 0x10000>;
+ #gpio-cells = <3>;
+ };
+
+ pmc@d8130000 {
+ compatible = "via,vt8500-pmc";
+ reg = <0xd8130000 0x1000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ref24: ref24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+ };
+
+ timer@d8130100 {
+ compatible = "via,vt8500-timer";
+ reg = <0xd8130100 0x28>;
+ interrupts = <36>;
+ };
+
+ ehci@d8007900 {
+ compatible = "via,vt8500-ehci";
+ reg = <0xd8007900 0x200>;
+ interrupts = <43>;
+ };
+
+ uhci@d8007b00 {
+ compatible = "platform-uhci";
+ reg = <0xd8007b00 0x200>;
+ interrupts = <43>;
+ };
+
+ fb@d800e400 {
+ compatible = "via,vt8500-fb";
+ reg = <0xd800e400 0x400>;
+ interrupts = <12>;
+ display = <&display>;
+ default-mode = <&mode0>;
+ };
+
+ ge_rops@d8050400 {
+ compatible = "wm,prizm-ge-rops";
+ reg = <0xd8050400 0x100>;
+ };
+
+ uart@d8200000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd8200000 0x1040>;
+ interrupts = <32>;
+ clocks = <&ref24>;
+ };
+
+ uart@d82b0000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd82b0000 0x1040>;
+ interrupts = <33>;
+ clocks = <&ref24>;
+ };
+
+ uart@d8210000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd8210000 0x1040>;
+ interrupts = <47>;
+ clocks = <&ref24>;
+ };
+
+ uart@d82c0000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd82c0000 0x1040>;
+ interrupts = <50>;
+ clocks = <&ref24>;
+ };
+
+ rtc@d8100000 {
+ compatible = "via,vt8500-rtc";
+ reg = <0xd8100000 0x10000>;
+ interrupts = <48>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
new file mode 100644
index 00000000000..fd4e248074c
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -0,0 +1,36 @@
+/*
+ * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8505.dtsi"
+
+/ {
+ model = "Wondermedia WM8505 Netbook";
+
+ /*
+ * Display node is based on Sascha Hauer's patch on dri-devel.
+ * Added a bpp property to calculate the size of the framebuffer
+ * until the binding is formalized.
+ */
+ display: display@0 {
+ modes {
+ mode0: mode@0 {
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <88>;
+ hfront-porch = <40>;
+ hsync-len = <0>;
+ vback-porch = <32>;
+ vfront-porch = <11>;
+ vsync-len = <1>;
+ clock = <0>; /* unused but required */
+ bpp = <32>; /* non-standard but required */
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
new file mode 100644
index 00000000000..b459691655a
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -0,0 +1,143 @@
+/*
+ * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "wm,wm8505";
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,arm926ejs";
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&intc0>;
+
+ intc0: interrupt-controller@d8140000 {
+ compatible = "via,vt8500-intc";
+ interrupt-controller;
+ reg = <0xd8140000 0x10000>;
+ #interrupt-cells = <1>;
+ };
+
+ /* Secondary IC cascaded to intc0 */
+ intc1: interrupt-controller@d8150000 {
+ compatible = "via,vt8500-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xD8150000 0x10000>;
+ interrupts = <56 57 58 59 60 61 62 63>;
+ };
+
+ gpio: gpio-controller@d8110000 {
+ compatible = "wm,wm8505-gpio";
+ gpio-controller;
+ reg = <0xd8110000 0x10000>;
+ #gpio-cells = <3>;
+ };
+
+ pmc@d8130000 {
+ compatible = "via,vt8500-pmc";
+ reg = <0xd8130000 0x1000>;
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ref24: ref24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+ };
+
+ timer@d8130100 {
+ compatible = "via,vt8500-timer";
+ reg = <0xd8130100 0x28>;
+ interrupts = <36>;
+ };
+
+ ehci@d8007100 {
+ compatible = "via,vt8500-ehci";
+ reg = <0xd8007100 0x200>;
+ interrupts = <43>;
+ };
+
+ uhci@d8007300 {
+ compatible = "platform-uhci";
+ reg = <0xd8007300 0x200>;
+ interrupts = <43>;
+ };
+
+ fb@d8050800 {
+ compatible = "wm,wm8505-fb";
+ reg = <0xd8050800 0x200>;
+ display = <&display>;
+ default-mode = <&mode0>;
+ };
+
+ ge_rops@d8050400 {
+ compatible = "wm,prizm-ge-rops";
+ reg = <0xd8050400 0x100>;
+ };
+
+ uart@d8200000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd8200000 0x1040>;
+ interrupts = <32>;
+ clocks = <&ref24>;
+ };
+
+ uart@d82b0000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd82b0000 0x1040>;
+ interrupts = <33>;
+ clocks = <&ref24>;
+ };
+
+ uart@d8210000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd8210000 0x1040>;
+ interrupts = <47>;
+ clocks = <&ref24>;
+ };
+
+ uart@d82c0000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd82c0000 0x1040>;
+ interrupts = <50>;
+ clocks = <&ref24>;
+ };
+
+ uart@d8370000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd8370000 0x1040>;
+ interrupts = <31>;
+ clocks = <&ref24>;
+ };
+
+ uart@d8380000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd8380000 0x1040>;
+ interrupts = <30>;
+ clocks = <&ref24>;
+ };
+
+ rtc@d8100000 {
+ compatible = "via,vt8500-rtc";
+ reg = <0xd8100000 0x10000>;
+ interrupts = <48>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
new file mode 100644
index 00000000000..cefd938f842
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -0,0 +1,36 @@
+/*
+ * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8650.dtsi"
+
+/ {
+ model = "Wondermedia WM8650-MID Tablet";
+
+ /*
+ * Display node is based on Sascha Hauer's patch on dri-devel.
+ * Added a bpp property to calculate the size of the framebuffer
+ * until the binding is formalized.
+ */
+ display: display@0 {
+ modes {
+ mode0: mode@0 {
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <88>;
+ hfront-porch = <40>;
+ hsync-len = <0>;
+ vback-porch = <32>;
+ vfront-porch = <11>;
+ vsync-len = <1>;
+ clock = <0>; /* unused but required */
+ bpp = <16>; /* non-standard but required */
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
new file mode 100644
index 00000000000..83b9467559b
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -0,0 +1,147 @@
+/*
+ * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "wm,wm8650";
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&intc0>;
+
+ intc0: interrupt-controller@d8140000 {
+ compatible = "via,vt8500-intc";
+ interrupt-controller;
+ reg = <0xd8140000 0x10000>;
+ #interrupt-cells = <1>;
+ };
+
+ /* Secondary IC cascaded to intc0 */
+ intc1: interrupt-controller@d8150000 {
+ compatible = "via,vt8500-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xD8150000 0x10000>;
+ interrupts = <56 57 58 59 60 61 62 63>;
+ };
+
+ gpio: gpio-controller@d8110000 {
+ compatible = "wm,wm8650-gpio";
+ gpio-controller;
+ reg = <0xd8110000 0x10000>;
+ #gpio-cells = <3>;
+ };
+
+ pmc@d8130000 {
+ compatible = "via,vt8500-pmc";
+ reg = <0xd8130000 0x1000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ref25: ref25M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ ref24: ref24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ plla: plla {
+ #clock-cells = <0>;
+ compatible = "wm,wm8650-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x200>;
+ };
+
+ pllb: pllb {
+ #clock-cells = <0>;
+ compatible = "wm,wm8650-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x204>;
+ };
+
+ arm: arm {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&plla>;
+ divisor-reg = <0x300>;
+ };
+
+ sdhc: sdhc {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x328>;
+ divisor-mask = <0x3f>;
+ enable-reg = <0x254>;
+ enable-bit = <18>;
+ };
+ };
+ };
+
+ timer@d8130100 {
+ compatible = "via,vt8500-timer";
+ reg = <0xd8130100 0x28>;
+ interrupts = <36>;
+ };
+
+ ehci@d8007900 {
+ compatible = "via,vt8500-ehci";
+ reg = <0xd8007900 0x200>;
+ interrupts = <43>;
+ };
+
+ uhci@d8007b00 {
+ compatible = "platform-uhci";
+ reg = <0xd8007b00 0x200>;
+ interrupts = <43>;
+ };
+
+ fb@d8050800 {
+ compatible = "wm,wm8505-fb";
+ reg = <0xd8050800 0x200>;
+ display = <&display>;
+ default-mode = <&mode0>;
+ };
+
+ ge_rops@d8050400 {
+ compatible = "wm,prizm-ge-rops";
+ reg = <0xd8050400 0x100>;
+ };
+
+ uart@d8200000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd8200000 0x1040>;
+ interrupts = <32>;
+ clocks = <&ref24>;
+ };
+
+ uart@d82b0000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd82b0000 0x1040>;
+ interrupts = <33>;
+ clocks = <&ref24>;
+ };
+
+ rtc@d8100000 {
+ compatible = "via,vt8500-rtc";
+ reg = <0xd8100000 0x10000>;
+ interrupts = <48>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xenvm-4.2.dts
new file mode 100644
index 00000000000..ec3f9528e18
--- /dev/null
+++ b/arch/arm/boot/dts/xenvm-4.2.dts
@@ -0,0 +1,68 @@
+/*
+ * Xen Virtual Machine for unprivileged guests
+ *
+ * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ model = "XENVM-4.2";
+ compatible = "xen,xenvm-4.2", "xen,xenvm";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ /* this field is going to be adjusted by the hypervisor */
+ bootargs = "console=hvc0 root=/dev/xvda";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* this field is going to be adjusted by the hypervisor */
+ reg = <0 0x80000000 0 0x08000000>;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x2c001000 0 0x1000>,
+ <0 0x2c002000 0 0x100>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ hypervisor {
+ compatible = "xen,xen-4.2", "xen,xen";
+ /* this field is going to be adjusted by the hypervisor */
+ reg = <0 0xb0000000 0 0x20000>;
+ /* this field is going to be adjusted by the hypervisor */
+ interrupts = <1 15 0xf08>;
+ };
+
+ motherboard {
+ arm,v2m-memory-map = "rs1";
+ };
+};