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authorJongsung Kim <neidhard.kim@lge.com>2013-05-29 22:07:39 -0600
committerOlof Johansson <olof@lixom.net>2013-06-02 11:50:41 -0700
commit13731d862cf5219216533a3b0de052cee4cc5038 (patch)
tree9717cd08378c708b4c03af3206bdc9e6ffa32ae8 /arch/arm/boot/dts
parent04b5e56fc31bac04517ba7fc801736ba99088082 (diff)
downloadvexpress-lsk-13731d862cf5219216533a3b0de052cee4cc5038.tar.gz
ARM: bcm2835: override the HW UART periphid
Stephen Warren reported the recent commit 78506f2 (add support for extended FIFO-size of PL011-r1p5) breaks the serial port on the BCM2835 ARM SoC. A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs. The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for this compatibility issue, this patch overrides the HW UART periphid register values with the actually compatible UART periphid 0x00241011 (r1p3 or r1p4). Reported-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jongsung Kim <neidhard.kim@lge.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index f0052dccf9a..1e12aeff403 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -44,6 +44,7 @@
reg = <0x7e201000 0x1000>;
interrupts = <2 25>;
clock-frequency = <3000000>;
+ arm,primecell-periphid = <0x00241011>;
};
gpio: gpio {