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authorSukanto Ghosh <sghosh@apm.com>2013-05-14 10:26:54 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-05-24 11:35:46 -0700
commitc2672f87c3b10f44e7e8f15f23d4dfec434c9053 (patch)
tree9dec2f681676c1fb52193deb0c9df138f8f4962d
parent71b86dfc5ed5a27c6d02eff2957587b8a00ae3dd (diff)
downloadvexpress-lsk-c2672f87c3b10f44e7e8f15f23d4dfec434c9053.tar.gz
arm64: mm: Fix operands of clz in __flush_dcache_all
commit b4fed0796841b5293b9c9427a5391b7bb20ef2d9 upstream. The format of the lower 32-bits of the 64-bit operand to 'dc cisw' is unchanged from ARMv7 architecture and the upper bits are RES0. This implies that the 'way' field of the operand of 'dc cisw' occupies the bit-positions [31 .. (32-A)]. Due to the use of 64-bit extended operands to 'clz', the existing implementation of __flush_dcache_all is incorrectly placing the 'way' field in the bit-positions [63 .. (64-A)]. Signed-off-by: Sukanto Ghosh <sghosh@apm.com> Tested-by: Anup Patel <anup.patel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--arch/arm64/mm/cache.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index abe69b80cf7..48a386094fa 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -52,7 +52,7 @@ loop1:
add x2, x2, #4 // add 4 (line length offset)
mov x4, #0x3ff
and x4, x4, x1, lsr #3 // find maximum number on the way size
- clz x5, x4 // find bit position of way size increment
+ clz w5, w4 // find bit position of way size increment
mov x7, #0x7fff
and x7, x7, x1, lsr #13 // extract max number of the index size
loop2: