path: root/arch/arm/include/asm
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authorDave Martin <dave.martin@linaro.org>2011-02-09 12:06:59 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-02-10 15:30:51 +0000
commit917692f5f7ec63de3b093c825913d68e910db282 (patch)
treed4f2a59ca417c446450df0c1a84384fcef501c7f /arch/arm/include/asm
parent774c096bf9e49eebf7b5d2d9fdddf632c29ccea0 (diff)
ARM: 6655/1: Correct WFE() in asm/spinlock.h for Thumb-2
The content for ALT_SMP() in the definition of WFE() expands to 6 bytes (IT cc ; WFEcc.W), which breaks the assumptions of the fixup code, leading to lockups when the affected code gets run. This patch works around the problem by explicitly using an IT + WFEcc.N pair. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm')
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index da1af524015..fdd3820edff 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -18,7 +18,23 @@
#define SEV ALT_SMP("sev.w", "nop.w")
-#define WFE(cond) ALT_SMP("wfe" cond ".w", "nop.w")
+ * For Thumb-2, special care is needed to ensure that the conditional WFE
+ * instruction really does assemble to exactly 4 bytes (as required by
+ * the SMP_ON_UP fixup code). By itself "wfene" might cause the
+ * assembler to insert a extra (16-bit) IT instruction, depending on the
+ * presence or absence of neighbouring conditional instructions.
+ *
+ * To avoid this unpredictableness, an approprite IT is inserted explicitly:
+ * the assembler won't change IT instructions which are explicitly present
+ * in the input.
+ */
+#define WFE(cond) ALT_SMP( \
+ "it " cond "\n\t" \
+ "wfe" cond ".n", \
+ \
+ "nop.w" \
#define SEV ALT_SMP("sev", "nop")
#define WFE(cond) ALT_SMP("wfe" cond, "nop")