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authorSteve Capper <steve.capper@linaro.org>2013-04-10 15:52:46 +0100
committerSteve Capper <steve.capper@linaro.org>2013-09-10 11:55:15 +0100
commit7d4a0fcbf668e2a6926626eeef3797990605ddba (patch)
treec0501245e96ad52e4fb8c3102b7ca62f77a1ef06 /tests/icache-hygiene.c
parent216510ca227db4f084cb348ed11487f68e69a3af (diff)
downloadlibhugetlbfs-7d4a0fcbf668e2a6926626eeef3797990605ddba.tar.gz
Aarch64 unit test fixes.
On Aarch64, zero bytes are illegal instructions, this is added to the icache-hygiene test. In mremap-expand-slice-collision, if __LP64__ is defined then mappings are attempted at 1TB boundaries which are outside the allowable mmap region for Aarch64. For __aarch64__ we change this mapping back to 256MB slices. Signed-off-by: Steve Capper <steve.capper@linaro.org>
Diffstat (limited to 'tests/icache-hygiene.c')
-rw-r--r--tests/icache-hygiene.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/tests/icache-hygiene.c b/tests/icache-hygiene.c
index 51792b3..876ce10 100644
--- a/tests/icache-hygiene.c
+++ b/tests/icache-hygiene.c
@@ -54,7 +54,7 @@ static void cacheflush(void *p)
{
#if defined(__powerpc__)
asm volatile("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r"(p));
-#elif defined(__arm__)
+#elif defined(__arm__) || defined(__aarch64__)
__clear_cache(p, p + COPY_SIZE);
#endif
}
@@ -87,8 +87,9 @@ static void *sig_expected;
static void sig_handler(int signum, siginfo_t *si, void *uc)
{
#if defined(__powerpc__) || defined(__powerpc64__) || defined(__ia64__) || \
- defined(__s390__) || defined(__s390x__) || defined(__sparc__)
- /* On powerpc and ia64 and s390, 0 bytes are an illegal
+ defined(__s390__) || defined(__s390x__) || defined(__sparc__) || \
+ defined(__aarch64__)
+ /* On powerpc, ia64, s390 and Aarch64, 0 bytes are an illegal
* instruction, so, if the icache is cleared properly, we SIGILL
* as soon as we jump into the cleared page */
if (signum == SIGILL) {