diff options
| -rw-r--r-- | drivers/iio/light/adux1020.c | 990 |
1 files changed, 990 insertions, 0 deletions
diff --git a/drivers/iio/light/adux1020.c b/drivers/iio/light/adux1020.c new file mode 100644 index 000000000000..ec78d80bd3bd --- /dev/null +++ b/drivers/iio/light/adux1020.c @@ -0,0 +1,990 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * adux1020.c - Support for Analog Devices ADUX1020 photometric sensor + * + * Copyright (C) 2019 Linaro Ltd. + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/mutex.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/iio/iio.h> +#include <linux/iio/buffer.h> +#include <linux/iio/events.h> +#include <linux/iio/kfifo_buf.h> +#include <linux/iio/sysfs.h> +#include <linux/of_gpio.h> + +#define ADUX1020_REGMAP_NAME "adux1020_regmap" +#define ADUX1020_DRV_NAME "adux1020" + +/* Data registers */ +#define ADUX1020_REG_READX1 0x00 +#define ADUX1020_REG_READX2 0x01 +#define ADUX1020_REG_READY1 0x02 +#define ADUX1020_REG_READY2 0x03 +#define ADUX1020_REG_SAMPLEI 0x04 +#define ADUX1020_REG_SAMPLEX 0x05 +#define ADUX1020_REG_SAMPLEY 0x06 + +/* System registers */ +#define ADUX1020_REG_CHIP_ID 0x08 +#define ADUX1020_REG_SLAVE_ADDRESS 0x09 + +/* Timer Test registers */ +#define ADUX1020_REG_OSC_CAL_OUT 0x0a + +/* Reset regiseter */ +#define ADUX1020_REG_SW_RESET 0x0f + +#define ADUX1020_REG_OSCS_1 0x18 +#define ADUX1020_REG_OSCS_3 0x1a +#define ADUX1020_REG_INT_ENABLE 0x1c +#define ADUX1020_REG_INT_POLARITY 0x1d +#define ADUX1020_REG_I2C_1 0x1e +#define ADUX1020_REG_I2C_2 0x1f +#define ADUX1020_REG_GEST_LED_WIDTH 0x20 +#define ADUX1020_REG_GEST_LED_PERIOD 0x21 +#define ADUX1020_REG_PROX_LED_WIDTH 0x22 +#define ADUX1020_REG_PROX_LED_PERIOD 0x23 +#define ADUX1020_REG_GEST_AFE 0x25 +#define ADUX1020_REG_PROX_AFE 0x26 +#define ADUX1020_REG_GEST_DI_TH 0x28 +#define ADUX1020_REG_GEST_ORIEN_NPTS 0x29 +#define ADUX1020_REG_PROX_TH_ON1 0x2a +#define ADUX1020_REG_PROX_TH_OFF1 0x2b +#define ADUX1020_REG_PROX_TH_ON2 0x2c +#define ADUX1020_REG_PROX_TH_OFF2 0x2d +#define ADUX1020_REG_PROX_TYPE 0x2f +#define ADUX1020_REG_TEST_MODES_1 0x30 +#define ADUX1020_REG_TEST_MODES_3 0x32 + +#define ADUX1020_REG_FORCE_MODE 0x33 +#define ADUX1020_REG_CH1_OFFSET 0x3a +#define ADUX1020_REG_CH2_OFFSET 0x3b +#define ADUX1020_REG_CH3_OFFSET 0x3c +#define ADUX1020_REG_CH4_OFFSET 0x3d +#define ADUX1020_REG_FREQUENCY 0x40 +#define ADUX1020_REG_LED_CURRENT 0x41 +#define ADUX1020_REG_OP_MODE 0x45 +#define ADUX1020_REG_DECIMATION 0x46 +#define ADUX1020_REG_INT_MASK 0x48 +#define ADUX1020_REG_INT_STATUS 0x49 +#define ADUX1020_REG_DATA_BUFFER 0x60 + +/* Chip ID bits */ +#define ADUX1020_CHIP_ID_MASK GENMASK(11,0) +#define ADUX1020_CHIP_ID 0x03fc + +#define ADUX1020_MODE_OUT_PROX_I 1 +#define ADUX1020_MODE_OUT_PROX_XY 3 +#define ADUX1020_MODE_OUT_SAMPLE 4 +#define ADUX1020_MODE_OUT_SHIFT 4 + +/* Power down bits */ +#define ADUX1020_PWDN_REF BIT(10) +#define ADUX1020_PWDN_OS32M BIT(11) +#define ADUX1020_PWDN_LED BIT(12) +#define ADUX1020_PWDN_ADC BIT(13) + +#define ADUX1020_SW_RESET BIT(1) +#define ADUX1020_FIFO_FLUSH BIT(15) +#define ADUX1020_FREQ_MASK GENMASK(3, 0) +#define ADUX1020_OP_MODE_MASK GENMASK(3, 0) +#define ADUX1020_DATA_OUT_MODE_MASK GENMASK(7, 4) + +#define ADUX1020_MODE_INT_MASK GENMASK(7, 0) +#define ADUX1020_IE_MASK BIT(1) +#define ADUX1020_INT_POL_MASK BIT(5) +#define ADUX1020_INT_ENABLE 0x2096 +#define ADUX1020_INT_DISABLE 0x2090 +#define ADUX1020_PROX_INT_ENABLE 0x00f0 +#define ADUX1020_PROX_ON1_INT BIT(0) +#define ADUX1020_PROX_OFF1_INT BIT(1) +#define ADUX1020_PROX_ON2_INT BIT(2) +#define ADUX1020_PROX_OFF2_INT BIT(3) +#define ADUX1020_GEST_INT_ENABLE 0xef +#define ADUX1020_SAMPLE_INT_ENABLE 0xdf +#define ADUX1020_FIFO_INT_ENABLE 0x7f +#define ADUX1020_MODE_INT_DISABLE 0xff +#define ADUX1020_MODE_INT_STATUS_MASK GENMASK(7, 0) +#define ADUX1020_FIFO_STATUS_MASK GENMASK(15, 8) +#define ADUX1020_PROX_TYPE BIT(15) + +#define ADUX1020_INT_PROX_ON1 BIT(0) +#define ADUX1020_INT_PROX_OFF1 BIT(1) +#define ADUX1020_INT_PROX_ON2 BIT(2) +#define ADUX1020_INT_PROX_OFF2 BIT(3) +#define ADUX1020_INT_GEST BIT(4) +#define ADUX1020_INT_SAMPLE BIT(5) +#define ADUX1020_INT_WDOG BIT(6) +#define ADUX1020_INT_FIFO BIT(7) + +#define ADUX1020_FORCE_CLOCK_ON 0x0f4f +#define ADUX1020_FORCE_CLOCK_RESET 0x0040 +#define ADUX1020_ACTIVE_4_STATE 0x0008 + +#define ADUX1020_GEST_FREQ_MASK GENMASK(3, 0) +#define ADUX1020_GEST_FREQ_SHIFT 0 +#define ADUX1020_PROX_FREQ_MASK GENMASK(7, 4) +#define ADUX1020_PROX_FREQ_SHIFT 4 + +#define ADUX1020_LED_CURRENT_MASK GENMASK(3, 0) +#define ADUX1020_LED_PIREF_EN BIT(12) + +/* Operating modes */ +enum adux1020_op_modes { + ADUX1020_MODE_STANDBY, + ADUX1020_MODE_PROX_I, + ADUX1020_MODE_PROX_XY, + ADUX1020_MODE_GEST, + ADUX1020_MODE_SAMPLE, + ADUX1020_MODE_FORCE = 0x0e, + ADUX1020_MODE_IDLE = 0x0f, +}; + +struct adux1020_data { + struct i2c_client *client; + struct iio_dev *indio_dev; + struct mutex lock; + struct regmap *regmap; + + /* interrupt status */ + u16 int_status; + + /* gesture buffer */ + u16 buffer[4]; /* 4 16-bit channels */ + + u8 gesture_mode_running; +}; + +struct _adux1020_mode_data { + u8 bytes; + u8 buf_len; + u16 int_en; +}; + +static const struct _adux1020_mode_data adux1020_mode_data [] = { + [ADUX1020_MODE_PROX_I] = { + .bytes = 2, + .buf_len = 1, + .int_en = ADUX1020_PROX_INT_ENABLE, + }, + [ADUX1020_MODE_PROX_XY] = { + .bytes = 6, + .buf_len = 3, + .int_en = ADUX1020_PROX_INT_ENABLE, + }, + [ADUX1020_MODE_SAMPLE] = { + .bytes = 8, + .buf_len = 4, + .int_en = ADUX1020_SAMPLE_INT_ENABLE, + }, +}; + +static const struct regmap_config adux1020_regmap_config = { + .name = ADUX1020_REGMAP_NAME, + .reg_bits = 8, + .val_bits = 16, + .max_register = 0x6F, + .cache_type = REGCACHE_NONE, +}; + +static const int adux1020_def_conf[][2] = { + { 0x000c, 0x000f }, + { 0x0010, 0x1010 }, + { 0x0011, 0x004c }, + { 0x0012, 0x5f0c }, + { 0x0013, 0xada5 }, + { 0x0014, 0x0080 }, + { 0x0015, 0x0000 }, + { 0x0016, 0x0600 }, + { 0x0017, 0x0000 }, + { 0x0018, 0x2693 }, + { 0x0019, 0x0004 }, + { 0x001a, 0x4280 }, + { 0x001b, 0x0060 }, + { 0x001c, 0x2094 }, + { 0x001d, 0x0020 }, + { 0x001e, 0x0001 }, + { 0x001f, 0x0100 }, + { 0x0020, 0x0320 }, + { 0x0021, 0x0A13 }, + { 0x0022, 0x0320 }, + { 0x0023, 0x0113 }, + { 0x0024, 0x0000 }, + { 0x0025, 0x2412 }, + { 0x0026, 0x2412 }, + { 0x0027, 0x0022 }, + { 0x0028, 0x0000 }, + { 0x0029, 0x0300 }, + { 0x002a, 0x0700 }, + { 0x002b, 0x0600 }, + { 0x002c, 0x6000 }, + { 0x002d, 0x4000 }, + { 0x002e, 0x0000 }, + { 0x002f, 0x0000 }, + { 0x0030, 0x0000 }, + { 0x0031, 0x0000 }, + { 0x0032, 0x0040 }, + { 0x0033, 0x0008 }, + { 0x0034, 0xE400 }, + { 0x0038, 0x8080 }, + { 0x0039, 0x8080 }, + { 0x003a, 0x2000 }, + { 0x003b, 0x1f00 }, + { 0x003c, 0x2000 }, + { 0x003d, 0x2000 }, + { 0x003e, 0x0000 }, + { 0x0040, 0x8069 }, + { 0x0041, 0x1f2f }, + { 0x0042, 0x4000 }, + { 0x0043, 0x0000 }, + { 0x0044, 0x0008 }, + { 0x0046, 0x0000 }, + { 0x0048, 0x00ef }, + { 0x0049, 0x0000 }, + { 0x0045, 0x0000 }, +}; + +static const int adux1020_rate[][2] = { + { 0, 100000 }, + { 0, 200000 }, + { 0, 500000 }, + { 1, 0 }, + { 2, 0 }, + { 5, 0 }, + { 10, 0 }, + { 20, 0 }, + { 50, 0 }, + { 100, 0 }, + { 190, 0 }, + { 450, 0 }, + { 820, 0 }, + { 1400, 0 }, +}; + +static const int adux1020_led_current[][2] = { + { 0, 25000 }, + { 0, 40000 }, + { 0, 55000 }, + { 0, 70000 }, + { 0, 85000 }, + { 0, 100000 }, + { 0, 115000 }, + { 0, 130000 }, + { 0, 145000 }, + { 0, 160000 }, + { 0, 175000 }, + { 0, 190000 }, + { 0, 205000 }, + { 0, 220000 }, + { 0, 235000 }, + { 0, 250000 }, +}; + +void debug_reg(struct adux1020_data *data, unsigned int reg) +{ + int ret; + unsigned int status; + + ret = regmap_read(data->regmap, reg, &status); + if (ret < 0) + return; + + pr_info("Reg %04x: %04x\n", reg, (status & 0xFFFF)); +} + +static void adux1020_flush_fifo(struct adux1020_data *data) +{ + /* Force Idle mode */ + regmap_write(data->regmap, ADUX1020_REG_FORCE_MODE, ADUX1020_ACTIVE_4_STATE); + regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE, + ADUX1020_OP_MODE_MASK, ADUX1020_MODE_FORCE); + regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE, + ADUX1020_OP_MODE_MASK, ADUX1020_MODE_IDLE); + + /* Flush FIFO */ + regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3, + ADUX1020_FORCE_CLOCK_ON); + regmap_write(data->regmap, ADUX1020_REG_INT_STATUS, + ADUX1020_FIFO_FLUSH); + regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3, + ADUX1020_FORCE_CLOCK_RESET); +} + +static int adux1020_read_fifo(struct adux1020_data *data, u16 *buf, u8 buf_len) +{ + int i, ret = -EINVAL; + unsigned int regval; + + mutex_lock(&data->lock); + + debug_reg(data,ADUX1020_REG_OP_MODE); + regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3, + ADUX1020_FORCE_CLOCK_ON); + + for (i = 0; i < buf_len; i++) { + ret = regmap_read(data->regmap, ADUX1020_REG_DATA_BUFFER, ®val); + if (ret < 0) + return ret; + + buf[i] = le16_to_cpu(regval); + pr_info("Buffer: 0x%04x\n", buf[i]); + } + + regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3, + ADUX1020_FORCE_CLOCK_RESET); + + mutex_unlock(&data->lock); + + return ret; +} + +static void adux1020_set_mode(struct adux1020_data *data, + enum adux1020_op_modes mode) +{ + /* Switch to standby mode before changing the mode */ + regmap_write(data->regmap, ADUX1020_REG_OP_MODE, ADUX1020_MODE_STANDBY); + + /* Set data out and switch to the desired mode */ + if (mode == ADUX1020_MODE_PROX_I) { + regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE, + ADUX1020_DATA_OUT_MODE_MASK, + ADUX1020_MODE_OUT_PROX_I << ADUX1020_MODE_OUT_SHIFT); + regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE, + ADUX1020_OP_MODE_MASK, ADUX1020_MODE_PROX_I); + } else if (mode == ADUX1020_MODE_PROX_XY) { + regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE, + ADUX1020_DATA_OUT_MODE_MASK, + ADUX1020_MODE_OUT_PROX_XY << ADUX1020_MODE_OUT_SHIFT); + regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE, + ADUX1020_OP_MODE_MASK, ADUX1020_MODE_PROX_XY - 1); + } else if (mode == ADUX1020_MODE_SAMPLE) { + regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE, + ADUX1020_DATA_OUT_MODE_MASK, + ADUX1020_MODE_OUT_SAMPLE << ADUX1020_MODE_OUT_SHIFT); + regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE, + ADUX1020_OP_MODE_MASK, ADUX1020_MODE_SAMPLE - 1); + } +} + +static int adux1020_measure(struct adux1020_data *data, + enum adux1020_op_modes mode, + u16 *val) +{ + int ret, tries = 50; + unsigned int status; + + /* Disable INT pin as polling is going to be used */ + regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE, + ADUX1020_INT_DISABLE); + + /* Enable mode interrupt */ + regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK, + ADUX1020_MODE_INT_MASK, adux1020_mode_data[mode].int_en); + + while (tries--) { + ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS, &status); + if (ret < 0) + goto fail; + + status &= ADUX1020_FIFO_STATUS_MASK; + if (status >= adux1020_mode_data[mode].bytes) + break; + msleep(20); + } + + if (tries < 0) { + ret = -EIO; + goto fail; + } + + ret = adux1020_read_fifo(data, val, adux1020_mode_data[mode].buf_len); + if (ret < 0) + goto fail; + + /* Clear mode interrupt */ + regmap_write(data->regmap, ADUX1020_REG_INT_STATUS, + (~adux1020_mode_data[mode].int_en)); + /* Disable mode interrupts */ + regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK, + ADUX1020_MODE_INT_MASK, ADUX1020_MODE_INT_DISABLE); + +fail: + + return ret; +} + +static int adux1020_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct adux1020_data *data = iio_priv(indio_dev); + u16 buf[3]; + int ret = -EINVAL; + unsigned int regval; + + switch(mask) { + case IIO_CHAN_INFO_RAW: + switch (chan->type) { + case IIO_INTENSITY: + adux1020_set_mode(data, ADUX1020_MODE_PROX_I); + ret = adux1020_measure(data, ADUX1020_MODE_PROX_I, + buf); + if (ret < 0) + return ret; + + *val = buf[0]; + ret = IIO_VAL_INT; + break; + case IIO_CURRENT: + ret = regmap_read(data->regmap, ADUX1020_REG_LED_CURRENT, + ®val); + if (ret < 0) + return ret; + + regval = regval & ADUX1020_LED_CURRENT_MASK; + + *val = adux1020_led_current[regval][0]; + *val2 = adux1020_led_current[regval][1]; + + ret = IIO_VAL_INT_PLUS_MICRO; + break; + case IIO_PROXIMITY: + adux1020_set_mode(data, ADUX1020_MODE_PROX_XY); + ret = adux1020_measure(data, ADUX1020_MODE_PROX_XY, + buf); + if (ret < 0) + return ret; + + /* Y-coordinate */ + *val = buf[1]; + ret = IIO_VAL_INT; + break; + default: + break; + } + break; + case IIO_CHAN_INFO_SAMP_FREQ: + ret = regmap_read(data->regmap, ADUX1020_REG_FREQUENCY, + ®val); + if (ret < 0) + return ret; + + if (chan->type == IIO_INTENSITY || chan->type == IIO_PROXIMITY) + regval = (regval & ADUX1020_PROX_FREQ_MASK) >> + ADUX1020_PROX_FREQ_SHIFT; + + *val = adux1020_rate[regval][0]; + *val2 = adux1020_rate[regval][1]; + + ret = IIO_VAL_INT_PLUS_MICRO; + break; + default: + break; + } + + return ret; +}; + +static int adux1020_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct adux1020_data *data = iio_priv(indio_dev); + int i, ret = -EINVAL; + + switch(mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + if (chan->type == IIO_INTENSITY) { + for (i = 0; i < ARRAY_SIZE(adux1020_rate); i++) { + if ((val == adux1020_rate[i][0]) && + (val2 == adux1020_rate[i][1])) { + ret = regmap_update_bits(data->regmap, + ADUX1020_REG_FREQUENCY, + ADUX1020_PROX_FREQ_MASK, + i << ADUX1020_PROX_FREQ_SHIFT); + } + } + } + break; + case IIO_CHAN_INFO_RAW: + if (chan->type == IIO_CURRENT) { + for (i = 0; i < ARRAY_SIZE(adux1020_led_current); i++) { + if ((val == adux1020_led_current[i][0]) && + (val2 == adux1020_led_current[i][1])) { + ret = regmap_update_bits(data->regmap, + ADUX1020_REG_LED_CURRENT, + ADUX1020_LED_CURRENT_MASK, i); + } + } + } + break; + default: + break; + } + + return ret; +} + +static int adux1020_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, enum iio_event_type type, + enum iio_event_direction dir, int state) +{ + struct adux1020_data *data = iio_priv(indio_dev); + + regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE, + ADUX1020_INT_ENABLE); + + regmap_write(data->regmap, ADUX1020_REG_INT_POLARITY, 0); + + switch (chan->type) { + case IIO_INTENSITY: + if (dir == IIO_EV_DIR_RISING) { + regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK, + ADUX1020_PROX_ON1_INT, + state ? 0 : ADUX1020_PROX_ON1_INT); + regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK, + ADUX1020_PROX_ON2_INT, + state ? 0 : ADUX1020_PROX_ON2_INT); + } else { + regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK, + ADUX1020_PROX_OFF1_INT, + state ? 0 : ADUX1020_PROX_OFF1_INT); + regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK, + ADUX1020_PROX_OFF2_INT, + state ? 0 : ADUX1020_PROX_OFF2_INT); + } + + /* + * Trigger proximity interrupt when the intensity is above + * or below threshold + */ + regmap_update_bits(data->regmap, ADUX1020_REG_PROX_TYPE, + ADUX1020_PROX_TYPE, ADUX1020_PROX_TYPE); + + /* Set proximity mode */ + adux1020_set_mode(data, ADUX1020_MODE_PROX_I); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int adux1020_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, enum iio_event_type type, + enum iio_event_direction dir) +{ + struct adux1020_data *data = iio_priv(indio_dev); + int ret, mask; + unsigned int regval; + + switch (chan->type) { + case IIO_INTENSITY: + if (dir == IIO_EV_DIR_RISING) + mask = ADUX1020_PROX_ON1_INT; + else + mask = ADUX1020_PROX_OFF1_INT; + break; + default: + return -EINVAL; + } + + mutex_lock(&data->lock); + + ret = regmap_read(data->regmap, ADUX1020_REG_INT_MASK, ®val); + if (ret < 0) + return ret; + + mutex_unlock(&data->lock); + + return !(le16_to_cpu(regval) & mask); +} + +static int adux1020_read_thresh(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, enum iio_event_type type, + enum iio_event_direction dir, enum iio_event_info info, + int *val, int *val2) +{ + struct adux1020_data *data = iio_priv(indio_dev); + u8 reg; + int ret; + unsigned int regval; + + switch (chan->type) { + case IIO_INTENSITY: + if (dir == IIO_EV_DIR_RISING) + reg = ADUX1020_REG_PROX_TH_ON1; + else + reg = ADUX1020_REG_PROX_TH_OFF1; + break; + default: + return -EINVAL; + } + + ret = regmap_read(data->regmap, ADUX1020_REG_INT_MASK, ®val); + if (ret < 0) + return ret; + + *val = le16_to_cpu(regval); + + return IIO_VAL_INT; +} + +static int adux1020_write_thresh(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, enum iio_event_type type, + enum iio_event_direction dir, enum iio_event_info info, + int val, int val2) +{ + struct adux1020_data *data = iio_priv(indio_dev); + u8 reg; + + switch (chan->type) { + case IIO_INTENSITY: + if (dir == IIO_EV_DIR_RISING) + reg = ADUX1020_REG_PROX_TH_ON1; + else + reg = ADUX1020_REG_PROX_TH_OFF1; + break; + default: + return -EINVAL; + } + + /* Full scale threshold value is 0-65535 */ + if (val < 0 || val > 65535) + return -EINVAL; + + return regmap_write(data->regmap, reg, cpu_to_le16(val)); +} + +static const struct iio_event_spec adux1020_intensity_event[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_ENABLE), + }, + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_FALLING, + .mask_separate = BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_ENABLE), + }, +}; + +static const unsigned long adux1020_scan_masks[] = {0xf, 0}; + +#define ADUX1020_GESTURE_CHANNEL(_dir, _si) { \ + .type = IIO_PROXIMITY, \ + .channel = _si + 1, \ + .scan_index = _si, \ + .indexed = 1, \ + .scan_type = { \ + .sign = 'u', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ +} + +static const struct iio_chan_spec adux1020_channels[] = { + { + .type = IIO_INTENSITY, + .modified = 1, + .channel2 = IIO_MOD_LIGHT_IR, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .event_spec = adux1020_intensity_event, + .num_event_specs = ARRAY_SIZE(adux1020_intensity_event), + .indexed = 0, + .scan_index = -1, + }, + { + .type = IIO_CURRENT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .extend_name = "led", + .indexed = 0, + .scan_index = -1, + }, + { + .type = IIO_PROXIMITY, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .channel = 0, + .indexed = 0, + .scan_index = -1, + }, + ADUX1020_GESTURE_CHANNEL(X1, 0), + ADUX1020_GESTURE_CHANNEL(Y1, 1), + ADUX1020_GESTURE_CHANNEL(X2, 2), + ADUX1020_GESTURE_CHANNEL(Y2, 3), +}; + +static IIO_CONST_ATTR(sampling_frequency_available, + "0.1 0.2 0.5 1 2 5 10 20 50 100 190 450 820 1400"); + +static struct attribute *adux1020_attributes[] = { + &iio_const_attr_sampling_frequency_available.dev_attr.attr, + NULL +}; + +static const struct attribute_group adux1020_attribute_group = { + .attrs = adux1020_attributes, +}; + +static const struct iio_info adux1020_info = { + .attrs = &adux1020_attribute_group, + .read_raw = adux1020_read_raw, + .write_raw = adux1020_write_raw, + .read_event_config = adux1020_read_event_config, + .write_event_config = adux1020_write_event_config, + .read_event_value = adux1020_read_thresh, + .write_event_value = adux1020_write_thresh, +}; + +static irqreturn_t adux1020_interrupt_handler(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct adux1020_data *data = iio_priv(indio_dev); + int ret, status; + + ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS, &status); + if (ret < 0) + return ret; + + status &= ADUX1020_MODE_INT_STATUS_MASK; + pr_info("Interrupt! Status: 0x%04x\n", status); + + if (status & ADUX1020_INT_PROX_ON1) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + iio_get_time_ns(indio_dev)); + } + + if (status & ADUX1020_INT_PROX_OFF1) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_FALLING), + iio_get_time_ns(indio_dev)); + } + + if (status & ADUX1020_INT_SAMPLE) { + ret = adux1020_read_fifo(data, data->buffer, + adux1020_mode_data[ADUX1020_MODE_SAMPLE].buf_len); + if (ret < 0) + return ret; + + iio_push_to_buffers(data->indio_dev, data->buffer); + } + + /* Clear all interrupts */ + regmap_update_bits(data->regmap, ADUX1020_REG_INT_STATUS, + ADUX1020_MODE_INT_MASK, ADUX1020_MODE_INT_DISABLE); + + return IRQ_HANDLED; +} + +static int adux1020_buffer_postenable(struct iio_dev *indio_dev) +{ + struct adux1020_data *data = iio_priv(indio_dev); + + /* Enable INT pin */ + regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE, + ADUX1020_INT_ENABLE); + regmap_write(data->regmap, ADUX1020_REG_INT_POLARITY, 0); + + /* Enable gesture interrupt */ + regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK, + ADUX1020_MODE_INT_MASK, + adux1020_mode_data[ADUX1020_MODE_SAMPLE].int_en); + + /* Enable gesture mode */ + adux1020_set_mode(data, ADUX1020_MODE_SAMPLE); + + msleep(20); + debug_reg(data, ADUX1020_REG_INT_STATUS); + return 0; +} + +static int adux1020_buffer_predisable(struct iio_dev *indio_dev) +{ + struct adux1020_data *data = iio_priv(indio_dev); + + regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE, + ADUX1020_INT_DISABLE); + + /* Disable gesture interrupt */ + regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK, + ADUX1020_MODE_INT_MASK, + ~adux1020_mode_data[ADUX1020_MODE_SAMPLE].int_en); + + /* Disable gesture mode by entering idle mode */ + adux1020_set_mode(data, ADUX1020_MODE_IDLE); + + return 0; +} + +static const struct iio_buffer_setup_ops adux1020_buffer_setup_ops = { + .postenable = adux1020_buffer_postenable, + .predisable = adux1020_buffer_predisable, +}; + +static int adux1020_chip_init(struct adux1020_data *data) +{ + struct i2c_client *client = data->client; + int ret, i; + unsigned int val; + + ret = regmap_read(data->regmap, ADUX1020_REG_CHIP_ID, &val); + if (ret < 0) + return ret; + + val &= ADUX1020_CHIP_ID_MASK; + + if (val != ADUX1020_CHIP_ID) { + dev_err(&client->dev, "invalid chip id 0x%04x\n", val); + return -ENODEV; + }; + + pr_info("Detected ADUX1020 chip id: 0x%04x\n", val); + + /* Perform software reset */ + regmap_update_bits(data->regmap, ADUX1020_REG_SW_RESET, + ADUX1020_SW_RESET, ADUX1020_SW_RESET); + + /* Load default configuration */ + for (i = 0; i < ARRAY_SIZE(adux1020_def_conf); i++) + regmap_write(data->regmap, adux1020_def_conf[i][0], + adux1020_def_conf[i][1]); + + adux1020_flush_fifo(data); + + /* Use LED_IREF for proximity mode */ + regmap_update_bits(data->regmap, ADUX1020_REG_LED_CURRENT, + ADUX1020_LED_PIREF_EN, 0); + + /* Mask all interrupts */ +// regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK, +// ADUX1020_MODE_INT_MASK, ADUX1020_MODE_INT_DISABLE); + + return 0; +} + +static int adux1020_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct adux1020_data *data; + struct iio_buffer *buffer; + struct iio_dev *indio_dev; + int ret; + + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + buffer = devm_iio_kfifo_allocate(&client->dev); + if (!buffer) + return -ENOMEM; + + iio_device_attach_buffer(indio_dev, buffer); + + indio_dev->dev.parent = &client->dev; + indio_dev->info = &adux1020_info; + indio_dev->name = ADUX1020_DRV_NAME; + indio_dev->channels = adux1020_channels; + indio_dev->num_channels = ARRAY_SIZE(adux1020_channels); + indio_dev->available_scan_masks = adux1020_scan_masks; + indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE); + indio_dev->setup_ops = &adux1020_buffer_setup_ops; + + data = iio_priv(indio_dev); + i2c_set_clientdata(client, indio_dev); + + data->regmap = devm_regmap_init_i2c(client, &adux1020_regmap_config); + if (IS_ERR(data->regmap)) { + dev_err(&client->dev, "regmap initialization failed.\n"); + return PTR_ERR(data->regmap); + } + + data->client = client; + data->indio_dev = indio_dev; + mutex_init(&data->lock); + + ret = adux1020_chip_init(data); + if (ret) + goto err_out; + + if (client->irq) { + ret = devm_request_threaded_irq(&client->dev, client->irq, + NULL, adux1020_interrupt_handler, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + ADUX1020_DRV_NAME, indio_dev); + if (ret) { + dev_err(&client->dev, "irq request error %d\n", -ret); + goto err_out; + } + } + + ret = iio_device_register(indio_dev); + if (ret) { + dev_err(&client->dev, "Failed to register IIO device\n"); + goto err_out; + } + + return 0; + +err_out: + return ret; +} + +static int adux1020_remove(struct i2c_client *client) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(client); + struct adux1020_data *data = iio_priv(indio_dev); + + iio_device_unregister(indio_dev); + + return 0; +} + +static const struct i2c_device_id adux1020_id[] = { + { "adux1020", 0 }, + {} +}; +MODULE_DEVICE_TABLE(i2c, adux1020_id); + +static const struct of_device_id adux1020_of_match[] = { + { .compatible = "adi,adux1020" }, + { } +}; +MODULE_DEVICE_TABLE(of, adux1020_of_match); + +static struct i2c_driver adux1020_driver = { + .driver = { + .name = ADUX1020_DRV_NAME, + .of_match_table = adux1020_of_match, + }, + .probe = adux1020_probe, + .remove = adux1020_remove, + .id_table = adux1020_id, +}; +module_i2c_driver(adux1020_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); +MODULE_DESCRIPTION("ADUX1020 photometric sensor"); +MODULE_LICENSE("GPL"); |