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| author | Yu Chen <chenyu56@huawei.com> | 2018-10-27 17:58:15 +0800 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2018-11-28 15:36:50 +0530 |
| commit | b95ded590bfd9bc13c6fc8c69e4c8834f42839f9 (patch) | |
| tree | 7b2f8f314452fd66da0635efc0d3b754db8cd76e /drivers/phy/hisilicon/Makefile | |
| parent | 2d2f54dd58cdd3d07ee6c76e6dbc1d895018e1cf (diff) | |
| download | 96b-common-b95ded590bfd9bc13c6fc8c69e4c8834f42839f9.tar.gz | |
usb: dwc3: Add two quirks for Hisilicon Kirin Soc Platform
There are tow quirks for DesignWare USB3 DRD Core of Hisilicon Kirin Soc.
1)SPLIT_BOUNDARY_DISABLE should be set for Host mode
2)A GCTL soft reset should be executed when switch mode
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Signed-off-by: Yu Chen <chenyu56@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Diffstat (limited to 'drivers/phy/hisilicon/Makefile')
0 files changed, 0 insertions, 0 deletions