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authorDavid Daney <david.daney@cavium.com>2014-05-28 23:52:05 +0200
committerRalf Baechle <ralf@linux-mips.org>2014-05-30 21:01:10 +0200
commit6e5111636d0ad6deb65a8280fdcd49e4753e5aec (patch)
tree584875c1c3c662a29291b0833de7e526b0fcd5e8 /arch
parenta36d8225bceba4b7be47ade34d175945f85cffbc (diff)
download96b-common-6e5111636d0ad6deb65a8280fdcd49e4753e5aec.tar.gz
MIPS: Move system level config items from CPU_CAVIUM_OCTEON to CAVIUM_OCTEON_SOC
They are a property of the SoC not the CPU itself. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2f2020f56898..78b558f77f5c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -732,6 +732,11 @@ config CAVIUM_OCTEON_SOC
select ZONE_DMA32
select HOLES_IN_ZONE
select ARCH_REQUIRE_GPIOLIB
+ select LIBFDT
+ select USE_OF
+ select ARCH_SPARSEMEM_ENABLE
+ select SYS_SUPPORTS_SMP
+ select NR_CPUS_DEFAULT_16
help
This option supports all of the Octeon reference boards from Cavium
Networks. It builds a kernel that dynamically determines the Octeon
@@ -1410,16 +1415,11 @@ config CPU_SB1
config CPU_CAVIUM_OCTEON
bool "Cavium Octeon processor"
depends on SYS_HAS_CPU_CAVIUM_OCTEON
- select ARCH_SPARSEMEM_ENABLE
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_SMP
- select NR_CPUS_DEFAULT_16
select WEAK_ORDERING
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
- select LIBFDT
- select USE_OF
select USB_EHCI_BIG_ENDIAN_MMIO
select MIPS_L1_CACHE_SHIFT_7
help