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authorChristoph Hellwig <hch@lst.de>2018-07-19 06:02:29 -0700
committerStafford Horne <shorne@gmail.com>2018-07-21 13:49:48 +0900
commit1902cbcc8ba16b5481bd7d3d7759f471a6829842 (patch)
tree666295d9ff6eacd145dee515b14a08f78cf0973e /arch/openrisc
parent1e4b044d22517cae7047c99038abb444423243ca (diff)
download96b-common-1902cbcc8ba16b5481bd7d3d7759f471a6829842.tar.gz
openrisc: remove the sync_single_for_cpu DMA operation
openrisc does all the required cache maintainance at dma map time, and none at unmap time. It thus has to implement sync_single_for_device to match the map cace for buffer reuse, but there is no point in doing another invalidation in the sync_single_cpu_case, which in terms of cache maintainance is equivalent to the unmap case. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc')
-rw-r--r--arch/openrisc/kernel/dma.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
index ec7fd45704d2..47601274abf7 100644
--- a/arch/openrisc/kernel/dma.c
+++ b/arch/openrisc/kernel/dma.c
@@ -209,20 +209,6 @@ or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
}
static void
-or1k_sync_single_for_cpu(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction dir)
-{
- unsigned long cl;
- dma_addr_t addr = dma_handle;
- struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
-
- /* Invalidate the dcache for the requested range */
- for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size)
- mtspr(SPR_DCBIR, cl);
-}
-
-static void
or1k_sync_single_for_device(struct device *dev,
dma_addr_t dma_handle, size_t size,
enum dma_data_direction dir)
@@ -243,7 +229,6 @@ const struct dma_map_ops or1k_dma_map_ops = {
.unmap_page = or1k_unmap_page,
.map_sg = or1k_map_sg,
.unmap_sg = or1k_unmap_sg,
- .sync_single_for_cpu = or1k_sync_single_for_cpu,
.sync_single_for_device = or1k_sync_single_for_device,
};
EXPORT_SYMBOL(or1k_dma_map_ops);