path: root/arch/openrisc/configs
diff options
authorJan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>2015-11-04 17:26:10 +0100
committerStafford Horne <shorne@gmail.com>2017-11-03 14:01:15 +0900
commit4ee93d80ad73980826d582c7c37caa9597822001 (patch)
treeaae34814c80135a8a385269e9a9e07892e36ac61 /arch/openrisc/configs
parentc056718464512da06d7f65a27d5e4f1707b24c80 (diff)
openrisc: add cacheflush support to fix icache aliasing
On OpenRISC the icache does not snoop data stores. This can cause aliasing as reported by Jan. This patch fixes the issue to ensure icache is properly synchronized when code is written to memory. It supports both SMP and UP flushing. This supports dcache flush as well for architectures that do not support write-through caches; most OpenRISC implementations do implement write-through cache however. Dcache flushes are done only on a single core as OpenRISC dcaches all support snooping of bus stores. Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de> [shorne@gmail.com: Squashed patches and wrote commit message] Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/configs')
0 files changed, 0 insertions, 0 deletions