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authorLinus Torvalds <torvalds@linux-foundation.org>2017-09-09 14:48:21 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2017-09-09 14:48:21 -0700
commita59e57da49f7c3f3de8cf4b7568a0c6c82f5b242 (patch)
tree521ccae942f9d226409cadb5503f74f78858e0af /Documentation
parent0ce5c79f384b9f730cf03a1e464673ae906e7c89 (diff)
parentd1f936d73683a540227cca3aaecdb68b6c3d53c5 (diff)
download96b-common-a59e57da49f7c3f3de8cf4b7568a0c6c82f5b242.tar.gz
Merge tag 'for-linus-20170904' of git://git.infradead.org/linux-mtd
Pull MTD updates from Boris Brezillon: "General updates: - Constify pci_device_id in various drivers - Constify device_type - Remove pad control code from the Gemini driver - Use %pOF to print OF node full_name - Various fixes in the physmap_of driver - Remove unused vars in mtdswap - Check devm_kzalloc() return value in the spear_smi driver - Check clk_prepare_enable() return code in the st_spi_fsm driver - Create per MTD device debugfs enties NAND updates, from Boris Brezillon: - Fix memory leaks in the core - Remove unused NAND locking support - Rename nand.h into rawnand.h (preparing support for spi NANDs) - Use NAND_MAX_ID_LEN where appropriate - Fix support for 20nm Hynix chips - Fix support for Samsung and Hynix SLC NANDs - Various cleanup, improvements and fixes in the qcom driver - Fixes for bugs detected by various static code analysis tools - Fix mxc ooblayout definition - Add a new part_parsers to tmio and sharpsl platform data in order to define a custom list of partition parsers - Request the reset line in exclusive mode in the sunxi driver - Fix a build error in the orion-nand driver when compiled for ARMv4 - Allow 64-bit mvebu platforms to select the PXA3XX driver SPI NOR updates, from Cyrille Pitchen and Marek Vasut: - add support to the JEDEC JESD216B specification (SFDP tables). - add support to the Intel Denverton SPI flash controller. - fix error recovery for Spansion/Cypress SPI NOR memories. - fix 4-byte address management for the Aspeed SPI controller. - add support to some Microchip SST26 memory parts - remove unneeded pinctrl header Write a message for tag:" * tag 'for-linus-20170904' of git://git.infradead.org/linux-mtd: (74 commits) mtd: nand: complain loudly when chip->bits_per_cell is not correctly initialized mtd: nand: make Samsung SLC NAND usable again mtd: nand: tmio: Register partitions using the parsers mfd: tmio: Add partition parsers platform data mtd: nand: sharpsl: Register partitions using the parsers mtd: nand: sharpsl: Add partition parsers platform data mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller mtd: nand: qcom: support for IPQ4019 QPIC NAND controller dt-bindings: qcom_nandc: IPQ8074 QPIC NAND documentation dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation dt-bindings: qcom_nandc: fix the ipq806x device tree example mtd: nand: qcom: support for different DEV_CMD register offsets mtd: nand: qcom: QPIC data descriptors handling mtd: nand: qcom: enable BAM or ADM mode mtd: nand: qcom: erased codeword detection configuration mtd: nand: qcom: support for read location registers mtd: nand: qcom: support for passing flags in DMA helper functions mtd: nand: qcom: add BAM DMA descriptor handling mtd: nand: qcom: allocate BAM transaction mtd: nand: qcom: DMA mapping support for register read buffer ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/mtd/qcom_nandc.txt65
-rw-r--r--Documentation/driver-api/mtdnand.rst8
2 files changed, 63 insertions, 10 deletions
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 70dd5118a324..73d336befa08 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -1,11 +1,20 @@
* Qualcomm NAND controller
Required properties:
-- compatible: should be "qcom,ipq806x-nand"
+- compatible: must be one of the following:
+ * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
+ SoC and it uses ADM DMA
+ * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
+ IPQ4019 SoC and it uses BAM DMA
+ * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
+ IPQ8074 SoC and it uses BAM DMA
+
- reg: MMIO address range
- clocks: must contain core clock and always on clock
- clock-names: must contain "core" for the core clock and "aon" for the
always on clock
+
+EBI2 specific properties:
- dmas: DMA specifier, consisting of a phandle to the ADM DMA
controller node and the channel number to be used for
NAND. Refer to dma.txt and qcom_adm.txt for more details
@@ -16,6 +25,12 @@ Required properties:
- qcom,data-crci: must contain the ADM data type CRCI block instance
number specified for the NAND controller on the given
platform
+
+QPIC specific properties:
+- dmas: DMA specifier, consisting of a phandle to the BAM DMA
+ and the channel number to be used for NAND. Refer to
+ dma.txt, qcom_bam_dma.txt for more details
+- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
- #address-cells: <1> - subnodes give the chip-select number
- #size-cells: <0>
@@ -26,7 +41,6 @@ chip-selects which (may) contain NAND flash chips. Their properties are as
follows.
Required properties:
-- compatible: should contain "qcom,nandcs"
- reg: a single integer representing the chip-select
number (e.g., 0, 1, 2, etc.)
- #address-cells: see partition.txt
@@ -43,8 +57,8 @@ partition.txt for more detail.
Example:
-nand@1ac00000 {
- compatible = "qcom,ebi2-nandc";
+nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
clocks = <&gcc EBI2_CLK>,
@@ -59,8 +73,7 @@ nand@1ac00000 {
#address-cells = <1>;
#size-cells = <0>;
- nandcs@0 {
- compatible = "qcom,nandcs";
+ nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
@@ -84,3 +97,43 @@ nand@1ac00000 {
};
};
};
+
+nand-controller@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpicbam 0>,
+ <&qpicbam 1>,
+ <&qpicbam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+};
diff --git a/Documentation/driver-api/mtdnand.rst b/Documentation/driver-api/mtdnand.rst
index e9afa586d15e..2a5191b6d445 100644
--- a/Documentation/driver-api/mtdnand.rst
+++ b/Documentation/driver-api/mtdnand.rst
@@ -516,7 +516,7 @@ mirrored table is performed.
The most important field in the nand_bbt_descr structure is the
options field. The options define most of the table properties. Use the
-predefined constants from nand.h to define the options.
+predefined constants from rawnand.h to define the options.
- Number of bits per block
@@ -843,7 +843,7 @@ Chip option constants
Constants for chip id table
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-These constants are defined in nand.h. They are OR-ed together to
+These constants are defined in rawnand.h. They are OR-ed together to
describe the chip functionality::
/* Buswitdh is 16 bit */
@@ -865,7 +865,7 @@ describe the chip functionality::
Constants for runtime options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-These constants are defined in nand.h. They are OR-ed together to
+These constants are defined in rawnand.h. They are OR-ed together to
describe the functionality::
/* The hw ecc generator provides a syndrome instead a ecc value on read
@@ -956,7 +956,7 @@ developer. Each struct member has a short description which is marked
with an [XXX] identifier. See the chapter "Documentation hints" for an
explanation.
-.. kernel-doc:: include/linux/mtd/nand.h
+.. kernel-doc:: include/linux/mtd/rawnand.h
:internal:
Public Functions Provided