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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-23 18:49:32 +0530
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-23 18:49:32 +0530
commit6d5b64d08b4e3652e6e52e16bd61abc3dd173204 (patch)
treea992df841a5b78ad971380f12ee15783c469f867
parent93ae13d812c832fadc1b084036e55df0af078cb0 (diff)
download96b-common-meerkat96-csi.tar.gz
Add CSI supportmeerkat96-csi
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-rw-r--r--arch/arm/boot/dts/imx7d-meerkat96.dts201
-rw-r--r--arch/arm/boot/dts/imx7s.dtsi36
2 files changed, 189 insertions, 48 deletions
diff --git a/arch/arm/boot/dts/imx7d-meerkat96.dts b/arch/arm/boot/dts/imx7d-meerkat96.dts
index 2ac74583d6a8..97efdb93b4e6 100644
--- a/arch/arm/boot/dts/imx7d-meerkat96.dts
+++ b/arch/arm/boot/dts/imx7d-meerkat96.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2019 Linaro Ltd.
*/
@@ -66,6 +66,30 @@
regulator-ramp-delay = <6250>;
};
+ camera_vdddo_1v8: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdddo";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ camera_vdda_2v8: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdda";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ camera_vddd_1v5: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vddd";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -136,6 +160,30 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
+
+ camera0: ov5645@3c {
+ compatible = "ovti,ov5645";
+ reg = <0x3c>;
+ clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+ pinctrl-0 = <&pinctrl_cam0_reset &pinctrl_cam0_en>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov5645_0_out: endpoint {
+ remote-endpoint = <&ov5645_0_in>;
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ };
+ };
+ };
};
&i2c4 {
@@ -157,52 +205,30 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
- display = <&display1>;
-/*
- display1: display_name {
- bits-per-pixel = <16>;
- bus-width = <24>;
- video-ports = <0x230145>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <83500000>;
- hactive = <1280>;
- vactive = <720>;
- hfront-porch = <220>;
- hback-porch = <110>;
- hsync-len = <40>;
- vback-porch = <5>;
- vfront-porch = <21>;
- vsync-len = <5>;
- };
- };
- };
-*/
- display1: display {
- bits-per-pixel = <32>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <33500000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <164>;
- hback-porch = <89>;
- hsync-len = <10>;
- vback-porch = <23>;
- vfront-porch = <10>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- };
+ display = <&display1>;
+
+ display1: display {
+ bits-per-pixel = <16>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <33000000>;
+ hactive = <800>;
+ vactive = <600>;
+ hback-porch = <88>;
+ hfront-porch = <40>;
+ vback-porch = <23>;
+ vfront-porch = <1>;
+ hsync-len = <128>;
+ vsync-len = <4>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ de-active = <1>;
+ };
+ };
+ };
};
&uart1 {
@@ -294,6 +320,75 @@
};
};
+&gpr {
+ mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x14 0x00000010>;
+ };
+
+ csi_mux {
+ compatible = "video-mux";
+ mux-controls = <&mux 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_csi_mux>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ csi_mux_to_csi: endpoint {
+ remote-endpoint = <&csi_from_csi_mux>;
+ };
+ };
+ };
+};
+
+&csi {
+ status = "okay";
+
+ port {
+ csi_from_csi_mux: endpoint {
+ remote-endpoint = <&csi_mux_to_csi>;
+ };
+ };
+};
+
+&mipi_csi {
+ clock-frequency = <166000000>;
+ resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
+ reset-names = "mrst";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fsl,csis-hs-settle = <3>;
+
+ port@0 {
+ reg = <0>;
+
+ ov5645_0_in: endpoint {
+ remote-endpoint = <&ov5645_0_out>;
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_vc0_to_csi_mux: endpoint {
+ remote-endpoint = <&csi_mux_from_mipi_vc0>;
+ };
+ };
+};
+
&iomuxc {
imx7d-sdb {
pinctrl_bt_gpios: bt_gpios {
@@ -447,5 +542,17 @@
MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19
>;
};
+
+ pinctrl_cam0_reset: cam0_reset {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x14
+ >;
+ };
+
+ pinctrl_cam0_en: cam0_en {
+ fsl,pins = <
+ MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14
+ >;
+ };
};
};
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index e88f53a4c7f4..be3ed4d02051 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -497,7 +497,7 @@
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx7d-iomuxc-gpr",
- "fsl,imx6q-iomuxc-gpr", "syscon";
+ "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
reg = <0x30340000 0x10000>;
};
@@ -606,6 +606,12 @@
#address-cells = <1>;
#size-cells = <0>;
+ pgc_mipi_phy: pgc-power-domain@0 {
+ #power-domain-cells = <0>;
+ reg = <0>;
+ power-supply = <&reg_1p0d>;
+ };
+
pgc_pcie_phy: pgc-power-domain@1 {
#power-domain-cells = <0>;
reg = <1>;
@@ -696,6 +702,17 @@
status = "disabled";
};
+ csi: csi@30710000 {
+ compatible = "fsl,imx7-csi";
+ reg = <0x30710000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "axi", "mclk", "dcic";
+ status = "disabled";
+ };
+
lcdif: lcdif@30730000 {
compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
reg = <0x30730000 0x10000>;
@@ -705,6 +722,23 @@
clock-names = "pix", "axi";
status = "disabled";
};
+
+ mipi_csi: mipi-csi@30750000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "fsl,imx7-mipi-csi2";
+ reg = <0x30750000 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+ <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
+ <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+ clock-names = "pclk", "wrap", "phy";
+ clock-frequency = <166000000>;
+ power-domains = <&pgc_mipi_phy>;
+ phy-supply = <&reg_1p0d>;
+ fsl,csis-hs-settle = <3>;
+ };
};
aips3: aips-bus@30800000 {