path: root/drivers/irqchip/irq-renesas-intc-irqpin.c
diff options
authorLinus Torvalds <torvalds@linux-foundation.org>2013-12-22 11:13:02 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2013-12-22 11:13:02 -0800
commit93579aeec2093ff12b55491c655129431b63e3dd (patch)
treefe2def1033b4aada50a27788adce9a6506183504 /drivers/irqchip/irq-renesas-intc-irqpin.c
parentba8b844f1b47f003d8d0af94275dc5bc7ab9665d (diff)
parent95fcfa70f3bc4b3b82bf582fa5b24a39bdbd23ae (diff)
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "Much smaller batch of fixes this week. Biggest one is a revert of an OMAP display change that removed some non-DT pinmux code that was still needed for 3.13 to get DSI displays to work. There's also a fix that resolves some misdescribed GPIO controller resources on shmobile. The rest are mostly smaller fixes, a couple of MAINTAINERS updates, etc" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: Revert "ARM: OMAP2+: Remove legacy mux code for display.c" MAINTAINERS: Add keystone clock drivers MAINTAINERS: Add keystone git tree information ARM: s3c64xx: dt: Fix boot failure due to double clock initialization ARM: shmobile: r8a7790: Fix GPIO resources in DTS irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB
Diffstat (limited to 'drivers/irqchip/irq-renesas-intc-irqpin.c')
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
index 82cec63a9011..3ee78f02e5d7 100644
--- a/drivers/irqchip/irq-renesas-intc-irqpin.c
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -149,8 +149,9 @@ static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
int irq, int do_mask)
- int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
- int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
+ /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
+ int bitfield_width = 4;
+ int shift = 32 - (irq + 1) * bitfield_width;
intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
shift, bitfield_width,
@@ -159,8 +160,9 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
+ /* The SENSE register is assumed to be 32-bit. */
int bitfield_width = p->config.sense_bitfield_width;
- int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
+ int shift = 32 - (irq + 1) * bitfield_width;
dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);