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authorLinus Torvalds <torvalds@linux-foundation.org>2014-07-18 20:49:47 -1000
committerLinus Torvalds <torvalds@linux-foundation.org>2014-07-18 20:49:47 -1000
commitd614cb0bc3c991710a7bbb5496e990550cb08180 (patch)
tree6caf224acfca4d72e4109a30421bee77ef9f0155 /arch/arm/mach-mvebu/headsmp-a9.S
parent1b9f0efd61e37636b96f59da6755d8048eb9a785 (diff)
parent9637f30e6b7bc394c08fa9d27d63622f141142e9 (diff)
downloadlinux-stericsson-d614cb0bc3c991710a7bbb5496e990550cb08180.tar.gz
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "A smaller set of fixes this week, and all regression fixes: - a handful of issues fixed on at91 with common clock conversion - a set of fixes for Marvell mvebu (SMP, coherency, PM) - a clock fix for i.MX6Q. - ... and a SMP/hotplug fix for Exynos" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: EXYNOS: Fix core ID used by platsmp and hotplug code ARM: at91/dt: add missing clocks property to pwm node in sam9x5.dtsi ARM: at91/dt: fix usb0 clocks definition in sam9n12 dtsi ARM: at91: at91sam9x5: correct typo error for ohci clock ARM: clk-imx6q: parent lvds_sel input from upstream clock gates ARM: mvebu: Fix coherency bus notifiers by using separate notifiers ARM: mvebu: Fix the operand list in the inline asm of armada_370_xp_pmsu_idle_enter ARM: mvebu: fix SMP boot for Armada 38x and Armada 375 Z1 in big endian
Diffstat (limited to 'arch/arm/mach-mvebu/headsmp-a9.S')
-rw-r--r--arch/arm/mach-mvebu/headsmp-a9.S9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index 5925366bc03c..da5bb292b91c 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -15,6 +15,8 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
+
__CPUINIT
#define CPU_RESUME_ADDR_REG 0xf10182d4
@@ -22,13 +24,18 @@
.global armada_375_smp_cpu1_enable_code_end
armada_375_smp_cpu1_enable_code_start:
- ldr r0, [pc, #4]
+ARM_BE8(setend be)
+ adr r0, 1f
+ ldr r0, [r0]
ldr r1, [r0]
+ARM_BE8(rev r1, r1)
mov pc, r1
+1:
.word CPU_RESUME_ADDR_REG
armada_375_smp_cpu1_enable_code_end:
ENTRY(mvebu_cortex_a9_secondary_startup)
+ARM_BE8(setend be)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(mvebu_cortex_a9_secondary_startup)