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authorEvan Quan <evan.quan@amd.com>2019-11-14 16:58:31 +0800
committerAlex Deucher <alexander.deucher@amd.com>2019-11-20 18:40:21 -0500
commitd2a08e46215ccb0e8d7ea5011ff07abc43d79860 (patch)
tree41f2ef324c60e21196f865003dcbb56b5b02ac4d
parent355d991cb6ff6ae76b5e28b8edae144124c730e4 (diff)
downloadlinux-stericsson-d2a08e46215ccb0e8d7ea5011ff07abc43d79860.tar.gz
drm/amd/powerplay: correct fine grained dpm force level setting
For fine grained dpm, there is only two levels supported. However to reflect correctly the current clock frequency, there is an intermediate level faked. Thus on forcing level setting, we need to treat level 2 correctly as level 1. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/navi10_ppt.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 3ec5a10a7c4d..328e258a6895 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -759,6 +759,12 @@ static int navi10_force_clk_levels(struct smu_context *smu,
case SMU_UCLK:
case SMU_DCEFCLK:
case SMU_FCLK:
+ /* There is only 2 levels for fine grained DPM */
+ if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
+ soft_max_level = (soft_max_level >= 1 ? 1 : 0);
+ soft_min_level = (soft_min_level >= 1 ? 1 : 0);
+ }
+
ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
if (ret)
return size;