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authorChris Elmquist <chrise@sgi.com>2005-12-20 13:25:19 -0800
committerDavid S. Miller <davem@sunset.davemloft.net>2005-12-28 13:04:52 -0800
commit091465d7514893a55dcf63e420698b21159c39a7 (patch)
treecbfaedb45164d21d0d2f4af5efad2fc78dd37f92
parent67dbb4ea33731415fe09c62149a34f472719ac1d (diff)
downloadlinux-stericsson-091465d7514893a55dcf63e420698b21159c39a7.tar.gz
[TG3]: ethtool -d hangs PCIe systems
Resubmitting after recommendation to use GET_REG32_1() instead of GET_REG32_LOOP(..., 1). Retested. Problem remains fixed. Prevent tg3_get_regs() from reading reserved and undocumented registers at RX_CPU_BASE and TX_CPU_BASE offsets which caused hostile behavior on PCIe platforms. Acked-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/tg3.c9
-rw-r--r--drivers/net/tg3.h7
2 files changed, 14 insertions, 2 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index cefb0c08a68d..ce252c58b3e7 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7151,8 +7151,13 @@ do { p = (u32 *)(orig_p + (reg)); \
GET_REG32_LOOP(BUFMGR_MODE, 0x58);
GET_REG32_LOOP(RDMAC_MODE, 0x08);
GET_REG32_LOOP(WDMAC_MODE, 0x08);
- GET_REG32_LOOP(RX_CPU_BASE, 0x280);
- GET_REG32_LOOP(TX_CPU_BASE, 0x280);
+ GET_REG32_1(RX_CPU_MODE);
+ GET_REG32_1(RX_CPU_STATE);
+ GET_REG32_1(RX_CPU_PGMCTR);
+ GET_REG32_1(RX_CPU_HWBKPT);
+ GET_REG32_1(TX_CPU_MODE);
+ GET_REG32_1(TX_CPU_STATE);
+ GET_REG32_1(TX_CPU_PGMCTR);
GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
GET_REG32_LOOP(FTQ_RESET, 0x120);
GET_REG32_LOOP(MSGINT_MODE, 0x0c);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 94dbcf3537ec..890e1635996b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1124,7 +1124,14 @@
/* 0x280 --> 0x400 unused */
#define RX_CPU_BASE 0x00005000
+#define RX_CPU_MODE 0x00005000
+#define RX_CPU_STATE 0x00005004
+#define RX_CPU_PGMCTR 0x0000501c
+#define RX_CPU_HWBKPT 0x00005034
#define TX_CPU_BASE 0x00005400
+#define TX_CPU_MODE 0x00005400
+#define TX_CPU_STATE 0x00005404
+#define TX_CPU_PGMCTR 0x0000541c
/* Mailboxes */
#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */