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path: root/drivers/acpi/plat/arm-core.c
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/*
 *  ARM/ARM64 Specific Low-Level ACPI Boot Support
 *
 *  Copyright (C) 2013, Al Stone <al.stone@linaro.org>
 *  Copyright (C) 2013, Graeme Gregory <graeme.gregory@linaro.org>
 *  Copyright (C) 2013, Hanjun Guo <hanjun.guo@linaro.org>
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 */

#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/cpumask.h>
#include <linux/memblock.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/bootmem.h>
#include <linux/smp.h>

#include <asm/pgtable.h>
#include <asm/cputype.h>

/*
 * We never plan to use RSDT on arm/arm64 as its deprecated in spec but this
 * variable is still required by the ACPI core
 */
u32 acpi_rsdt_forced;

int acpi_noirq;			/* skip ACPI IRQ initialization */
int acpi_strict;
int acpi_disabled;
EXPORT_SYMBOL(acpi_disabled);

int acpi_pci_disabled;		/* skip ACPI PCI scan and IRQ initialization */
EXPORT_SYMBOL(acpi_pci_disabled);

/* available_cpus here means enabled cpu in MADT */
static int available_cpus;

/* Map logic cpu id to physical GIC id (physical CPU id). */
int arm_cpu_to_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = -1 };
static int boot_cpu_apic_id = -1;

/* Parked Address in ACPI GIC structure */
static u64 parked_address[NR_CPUS];

#define PREFIX			"ACPI: "

/* FIXME: this function should be moved to topology.c when it is ready */
void arch_fix_phys_package_id(int num, u32 slot)
{
	return;
}
EXPORT_SYMBOL_GPL(arch_fix_phys_package_id);

/*
 * Since we're on ARM, the default interrupt routing model
 * clearly has to be GIC.
 */
enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_GIC;

static unsigned int gsi_to_irq(unsigned int gsi)
{
	int irq = irq_find_mapping(NULL, gsi);

	return irq;
}

/*
 * __acpi_map_table() will be called before page_init(), so early_ioremap()
 * or early_memremap() should be called here.
 *
 * FIXME: early_io/memremap()/early_iounmap() are not upstream yet on ARM64,
 * just wait for Mark Salter's patchset accepted by mainline
 */
char *__init __acpi_map_table(unsigned long phys, unsigned long size)
{
	if (!phys || !size)
		return NULL;

	/*
	 * temporarily use phys_to_virt(),
	 * should be early_memremap(phys, size) here
	 */
	return phys_to_virt(phys);
}

void __init __acpi_unmap_table(char *map, unsigned long size)
{
	if (!map || !size)
		return;

	/* should be early_iounmap(map, size); */
	return;
}

static int __init acpi_parse_madt(struct acpi_table_header *table)
{
	struct acpi_table_madt *madt = NULL;

	madt = (struct acpi_table_madt *)table;
	if (!madt) {
		pr_warn(PREFIX "Unable to map MADT\n");
		return -ENODEV;
	}

	return 0;
}

/**
 * acpi_register_gic_cpu_interface - register a gic cpu interface and
 * generates a logic cpu number
 * @id: gic cpu interface id to register
 * @enabled: this cpu is enabled or not
 *
 * Returns the logic cpu number which maps to the gic cpu interface
 */
static int acpi_register_gic_cpu_interface(int id, u8 enabled)
{
	int cpu;

	if (id >= MAX_GIC_CPU_INTERFACE) {
		pr_info(PREFIX "skipped apicid that is too big\n");
		return -EINVAL;
	}

	total_cpus++;
	if (!enabled)
		return -EINVAL;

	if (available_cpus >=  NR_CPUS) {
		pr_warn(PREFIX "NR_CPUS limit of %d reached,"
		" Processor %d/0x%x ignored.\n", NR_CPUS, total_cpus, id);
		return -EINVAL;
	}

	available_cpus++;

	/* allocate a logic cpu id for the new comer */
	if (boot_cpu_apic_id == id) {
		/*
		 * boot_cpu_init() already hold bit 0 in cpu_present_mask
		 * for BSP, no need to allocte again.
		 */
		cpu = 0;
	} else {
		cpu = cpumask_next_zero(-1, cpu_present_mask);
	}

	/* map the logic cpu id to APIC id */
	arm_cpu_to_apicid[cpu] = id;

	set_cpu_present(cpu, true);
	set_cpu_possible(cpu, true);

	return cpu;
}

static int __init
acpi_parse_gic(struct acpi_subtable_header *header, const unsigned long end)
{
	struct acpi_madt_generic_interrupt *processor = NULL;
	int cpu;

	processor = (struct acpi_madt_generic_interrupt *)header;

	if (BAD_MADT_ENTRY(processor, end))
		return -EINVAL;

	acpi_table_print_madt_entry(header);

	/*
	 * We need to register disabled CPU as well to permit
	 * counting disabled CPUs. This allows us to size
	 * cpus_possible_map more accurately, to permit
	 * to not preallocating memory for all NR_CPUS
	 * when we use CPU hotplug.
	 */
	cpu = acpi_register_gic_cpu_interface(processor->gic_id,
			processor->flags & ACPI_MADT_ENABLED);

	/*
	 * We need the parked address for SMP initialization with
	 * spin-table enable method
	 */
	if (cpu >= 0 && processor->parked_address)
		parked_address[cpu] = processor->parked_address;

	return 0;
}

/*
 * Parse GIC cpu interface related entries in MADT
 * returns 0 on success, < 0 on error
 */
static int __init acpi_parse_madt_gic_entries(void)
{
	int count;
 
	/*
	 * do a partial walk of MADT to determine how many CPUs
	 * we have including disabled CPUs
	 */
	count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
				acpi_parse_gic, MAX_GIC_CPU_INTERFACE);

	if (!count) {
		pr_err(PREFIX "No GIC entries present\n");
		return -ENODEV;
	} else if (count < 0) {
		pr_err(PREFIX "Error parsing GIC entry\n");
		return count;
	}

#ifdef CONFIG_SMP
	if (available_cpus == 0) {
		pr_info(PREFIX "Found 0 CPUs; assuming 1\n");
		arm_cpu_to_apicid[available_cpus] =
			read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
		available_cpus = 1;	/* We've got at least one of these */
	}
#endif

	/* Make boot-up look pretty */
	pr_info("%d CPUs available, %d CPUs total\n", available_cpus,
		total_cpus);

	return 0;
}

int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
{
	*irq = gsi_to_irq(gsi);

	return 0;
}
EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);

int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi)
{
	return -1;
}

int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base)
{
	/* TBD */
	return -EINVAL;
}
EXPORT_SYMBOL(acpi_register_ioapic);

int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base)
{
	/* TBD */
	return -EINVAL;
}
EXPORT_SYMBOL(acpi_unregister_ioapic);

/*
 * success: return IRQ number (>0)
 * failure: return =< 0
 */
int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
{
	unsigned int irq;
	unsigned int irq_type;

	/*
	 * ACPI have no bindings to indicate SPI or PPI, so we
	 * use different mappings from DT in ACPI.
	 *
	 * For FDT
	 * PPI interrupt: in the range [0, 15];
	 * SPI interrupt: in the range [0, 987];
	 *
	 * For ACPI, GSI should be unique so using
	 * identity mapping for hwirq:
	 * PPI interrupt: in the range [16, 31];
	 * SPI interrupt: in the range [32, 1019];
	 */

	if (trigger == ACPI_EDGE_SENSITIVE &&
				polarity == ACPI_ACTIVE_LOW)
		irq_type = IRQ_TYPE_EDGE_FALLING;
	else if (trigger == ACPI_EDGE_SENSITIVE &&
				polarity == ACPI_ACTIVE_HIGH)
		irq_type = IRQ_TYPE_EDGE_RISING;
	else if (trigger == ACPI_LEVEL_SENSITIVE &&
				polarity == ACPI_ACTIVE_LOW)
		irq_type = IRQ_TYPE_LEVEL_LOW;
	else if (trigger == ACPI_LEVEL_SENSITIVE &&
				polarity == ACPI_ACTIVE_HIGH)
		irq_type = IRQ_TYPE_LEVEL_HIGH;
	else
		irq_type = IRQ_TYPE_NONE;

	/*
	 * Since only one GIC is supported in ACPI 5.0, we can
	 * create mapping refer to the default domain
	 */
	irq = irq_create_mapping(NULL, gsi);
	if (!irq)
		return irq;

	/* Set irq type if specified and different than the current one */
	if (irq_type != IRQ_TYPE_NONE &&
		irq_type != irq_get_trigger_type(irq))
		irq_set_irq_type(irq, irq_type);
	return irq;
}
EXPORT_SYMBOL_GPL(acpi_register_gsi);

void acpi_unregister_gsi(u32 gsi)
{
}
EXPORT_SYMBOL_GPL(acpi_unregister_gsi);

static int __init acpi_parse_fadt(struct acpi_table_header *table)
{
	return 0;
}

static void __init acpi_process_madt(void)
{
	int error;

	/* Get the boot CPU interface ID before MADT parsing */
	boot_cpu_apic_id = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;

	if (!acpi_table_parse(ACPI_SIG_MADT, acpi_parse_madt)) {

		/*
		 * Parse MADT GIC cpu interface entries
		 */
		error = acpi_parse_madt_gic_entries();
		if (!error)
			pr_info("Using ACPI for processor (GIC) configuration information\n");
	}

	return;
}

/*
 * acpi_boot_table_init() and acpi_boot_init()
 *  called from setup_arch(), always.
 *	1. checksums all tables
 *	2. enumerates lapics
 *	3. enumerates io-apics
 *
 * acpi_table_init() is separated to allow reading SRAT without
 * other side effects.
 */
void __init acpi_boot_table_init(void)
{
	/*
	 * If acpi_disabled, bail out
	 */
	if (acpi_disabled)
		return;

	/*
	 * Initialize the ACPI boot-time table parser.
	 */
	if (acpi_table_init()) {
		disable_acpi();
		return;
	}
}

int __init acpi_boot_init(void)
{
	/*
	 * If acpi_disabled, bail out
	 */
	if (acpi_disabled)
		return -ENODEV;

	acpi_table_parse(ACPI_SIG_FADT, acpi_parse_fadt);

	/*
	 * Process the Multiple APIC Description Table (MADT), if present
	 */
	acpi_process_madt();

	return 0;
}

static int __init parse_acpi(char *arg)
{
	if (!arg)
		return -EINVAL;

	/* "acpi=off" disables both ACPI table parsing and interpreter */
	if (strcmp(arg, "off") == 0) {
		disable_acpi();
	}
	/* acpi=strict disables out-of-spec workarounds */
	else if (strcmp(arg, "strict") == 0) {
		acpi_strict = 1;
	}
	return 0;
}
early_param("acpi", parse_acpi);

/*
 * acpi_suspend_lowlevel() - save kernel state and suspend.
 *
 * TBD when ARM/ARM64 starts to support suspend...
 */
int (*acpi_suspend_lowlevel)(void);