aboutsummaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
authorshameer <shamiali2008@gmail.com>2017-05-20 19:45:10 +0100
committerGraeme Gregory <graeme.gregory@linaro.org>2017-06-06 10:00:44 +0100
commit37edf0f0978a06e825a1ef449183adf79d12deca (patch)
tree60fd3384814c8b615d90f44906834ebbd5e3b188 /drivers
parent0d2d2a67c95fd4304dd00b935a6695131e9ab12b (diff)
downloadleg-kernel-37edf0f0978a06e825a1ef449183adf79d12deca.tar.gz
KVM:arm/arm64: HiSilicon GIC quirk for kvm CPU stall issue
KVM uses virt-phys interrupt map feature while forwarding the timer interrupt to Guest (ICH_LR HW bit=1). At present GIC on HiSilicon platforms(D02/D03) has issues with this feature and causes CPU stall. This patch uses non mapped timer irq inject into the Guest. When Guest deactivates the timer irq, a maintenance EOI irq is generated and KVM handles the deactivation on phys distributor. Signed-off-by: shameer <shamiali2008@gmail.com> Remove dts and change matching to HIP05/HIP06 Disable pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu); There is a bug in D03 board that doesn't always clear interrupt, but this doesn't impact the functionality, so disable the warning. Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/irqchip/irq-gic-v3.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index c132f29322cc..19b95834cc05 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1100,6 +1100,10 @@ static void __init gic_of_setup_kvm_info(struct device_node *node)
if (!gic_v3_kvm_info.maint_irq)
return;
+ /* HiSilicon GIC quirk: virtual timer irq map not supported */
+ gic_v3_kvm_info.hisi_vtimer_quirk = of_property_read_bool(node,
+ "hisi-kvm-vtimer-quirk");
+
if (of_property_read_u32(node, "#redistributor-regions",
&gicv_idx))
gicv_idx = 1;
@@ -1378,6 +1382,29 @@ static bool __init gic_acpi_collect_virt_info(void)
#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
+static void __init acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+ /*
+ * Workaround for D02 and D03, disable virt timer interrupt
+ * mapping because GIC on D02 and D03 don't support that
+ */
+ if (!strncmp(oem_id, "HISI", 4) &&
+ (!strncmp(oem_table_id, "HIP05", 5) ||
+ !strncmp(oem_table_id, "HIP06", 5)))
+ gic_v3_kvm_info.hisi_vtimer_quirk = true;
+}
+
+static int __init acpi_parse_madt(struct acpi_table_header *table)
+{
+ struct acpi_table_madt *acpi_madt;
+
+ acpi_madt = (struct acpi_table_madt *)table;
+ acpi_madt_oem_check(acpi_madt->header.oem_id,
+ acpi_madt->header.oem_table_id);
+
+ return 0;
+}
+
static void __init gic_acpi_setup_kvm_info(void)
{
int irq;
@@ -1387,6 +1414,8 @@ static void __init gic_acpi_setup_kvm_info(void)
return;
}
+ acpi_table_parse(ACPI_SIG_MADT, acpi_parse_madt);
+
gic_v3_kvm_info.type = GIC_V3;
irq = acpi_register_gsi(NULL, acpi_data.maint_irq,