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authorPunit Agrawal <punit.agrawal@arm.com>2013-08-22 14:43:18 +0100
committerWill Deacon <will.deacon@arm.com>2013-09-17 12:02:15 +0100
commit83bc10a2754bf9f2e373fb884dd63ac061453187 (patch)
treedf0b4426d690a7f5eeeae7b475823dbbb11a6756 /Documentation/devicetree/bindings/arm/cci.txt
parentfcb20f15167dc33336cb53724ef67255db8401b4 (diff)
downloadleg-kernel-83bc10a2754bf9f2e373fb884dd63ac061453187.tar.gz
ARM: dts: Document the CCI PMU DT bindings
The CCI PMU can profile bus transactions at the master and slave interfaces of the CCI. The PMU can be used to observe an aggregated view of the bus traffic between the various components connected to the CCI. Introduce a binding for the CCI PMU. The PMU node will be a sub-node of the CCI node. Cc: devicetree@vger.kernel.org Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/cci.txt')
-rw-r--r--Documentation/devicetree/bindings/arm/cci.txt48
1 files changed, 47 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
index 024c03df051a..f28d82bbbc56 100644
--- a/Documentation/devicetree/bindings/arm/cci.txt
+++ b/Documentation/devicetree/bindings/arm/cci.txt
@@ -85,6 +85,42 @@ specific to ARM.
corresponding interface programming
registers.
+ - CCI PMU node
+
+ Parent node must be CCI interconnect node.
+
+ A CCI pmu node must contain the following properties:
+
+ - compatible
+ Usage: required
+ Value type: <string>
+ Definition: must be "arm,cci-400-pmu"
+
+ - reg:
+ Usage: required
+ Value type: Integer cells. A register entry, expressed
+ as a pair of cells, containing base and
+ size.
+ Definition: the base address and size of the
+ corresponding interface programming
+ registers.
+
+ - interrupts:
+ Usage: required
+ Value type: Integer cells. Array of interrupt specifier
+ entries, as defined in
+ ../interrupt-controller/interrupts.txt.
+ Definition: list of counter overflow interrupts, one per
+ counter. The interrupts must be specified
+ starting with the cycle counter overflow
+ interrupt, followed by counter0 overflow
+ interrupt, counter1 overflow interrupt,...
+ ,counterN overflow interrupt.
+
+ The CCI PMU has an interrupt signal for each
+ counter. The number of interrupts must be
+ equal to the number of counters.
+
* CCI interconnect bus masters
Description: masters in the device tree connected to a CCI port
@@ -150,7 +186,7 @@ Example:
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x2c090000 0 0x1000>;
- ranges = <0x0 0x0 0x2c090000 0x6000>;
+ ranges = <0x0 0x0 0x2c090000 0x10000>;
cci_control0: slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
@@ -169,6 +205,16 @@ Example:
interface-type = "ace";
reg = <0x5000 0x1000>;
};
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu";
+ reg = <0x9000 0x5000>;
+ interrupts = <0 101 4>,
+ <0 102 4>,
+ <0 103 4>,
+ <0 104 4>,
+ <0 105 4>;
+ };
};
This CCI node corresponds to a CCI component whose control registers sits