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authorTomasz Nowicki <tomasz.nowicki@linaro.org>2015-02-26 13:07:33 +0100
committerGraeme Gregory <graeme.gregory@linaro.org>2015-07-07 13:38:07 +0100
commit54ec779e461c60b4656f37f796bda5d294c74199 (patch)
treed3529c12f1b5f3d2b499b16301e0d2220b269d55
parentd8851d1b3bf5f89d2f390e3acfb9ca1d0d38241c (diff)
downloadleg-kernel-54ec779e461c60b4656f37f796bda5d294c74199.tar.gz
x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs.
- fix typo - improve explanation - add reference to the related document Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
-rw-r--r--arch/x86/include/asm/pci_x86.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index 164e3f8d3c3d..eddf8f05cfb5 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -154,10 +154,13 @@ extern struct list_head pci_mmcfg_list;
/*
* AMD Fam10h CPUs are buggy, and cannot access MMIO config space
- * on their northbrige except through the * %eax register. As such, you MUST
- * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
+ * on their northbridge except through the * %eax register. As such, you MUST
+ * NOT use normal IOMEM accesses, you need to only use the magic mmio_config_*
* accessor functions.
- * In fact just use pci_config_*, nothing else please.
+ *
+ * Please refer to the following doc:
+ * "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors",
+ * rev. 3.48, sec 2.11.1, "MMIO Configuration Coding Requirements".
*/
static inline unsigned char mmio_config_readb(void __iomem *pos)
{