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2014-05-23Merge pull request #102 from achingupta:ag/tf-issues#104-v2Andrew Thoelke
2014-05-23Merge pull request #100 from jcastillo-arm:jc/tf-issues/149-v4Andrew Thoelke
2014-05-22Introduce interrupt handling framework in BL3-1Achin Gupta
This patch adds a common handler for FIQ and IRQ exceptions in the BL3-1 runtime exception vector table. This function determines the interrupt type and calls its handler. A crash is reported if an inconsistency in the interrupt management framework is detected. In the event of a spurious interrupt, execution resumes from the instruction where the interrupt was generated. This patch also removes 'cm_macros.S' as its contents have been moved to 'runtime_exceptions.S' Change-Id: I3c85ecf8eaf43a3fac429b119ed0bd706d2e2093
2014-05-22Introduce interrupt registration framework in BL3-1Achin Gupta
This patch introduces a framework for registering interrupts routed to EL3. The interrupt routing model is governed by the SCR_EL3.IRQ and FIQ bits and the security state an interrupt is generated in. The framework recognizes three type of interrupts depending upon which exception level and security state they should be handled in i.e. Secure EL1 interrupts, Non-secure interrupts and EL3 interrupts. It provides an API and macros that allow a runtime service to register an handler for a type of interrupt and specify the routing model. The framework validates the routing model and uses the context management framework to ensure that it is applied to the SCR_EL3 prior to entry into the target security state. It saves the handler in internal data structures. An API is provided to retrieve the handler when an interrupt of a particular type is asserted. Registration is expected to be done once by the primary CPU. The same handler and routing model is used for all CPUs. Support for EL3 interrupts will be added to the framework in the future. A makefile flag has been added to allow the FVP port choose between ARM GIC v2 and v3 support in EL3. The latter version is currently unsupported. A framework for handling interrupts in BL3-1 will be introduced in subsequent patches. The default routing model in the absence of any handlers expects no interrupts to be routed to EL3. Change-Id: Idf7c023b34fcd4800a5980f2bef85e4b5c29e649
2014-05-22Doc: Add the "Building the Test Secure Payload" sectionSandrine Bailleux
Add a section in the user guide explaining how to compile the TSP image and include it into the FIP. This includes instructions to make the TSP run from Trusted DRAM (rather than Trusted SRAM) on FVP. Change-Id: I04780757a149eeb5482a12a61e821be947b882c0
2014-05-22Reserve some DDR DRAM for secure use on FVP platformsJuan Castillo
TZC-400 is configured to set the last 16MB of DRAM1 as secure memory and the rest of DRAM as non-secure. Non-secure software must not attempt to access the 16MB secure area. Device tree files (sources and binaries) have been updated to match this configuration, removing that memory from the Linux physical memory map. To use UEFI and Linux with this patch, the latest version of UEFI and the updated device tree files are required. Check the user guide in the documentation for more details. Replaced magic numbers with #define for memory region definition in the platform security initialization function. Fixes ARM-software/tf-issues#149 Change-Id: Ia5d070244aae6c5288ea0e6c8e89d92859522bfe
2014-05-16Add build configuration for timer save/restoreJeenu Viswambharan
At present, non-secure timer register contents are saved and restored as part of world switch by BL3-1. This effectively means that the non-secure timer stops, and non-secure timer interrupts are prevented from asserting until BL3-1 switches back, introducing latency for non-secure services. Often, secure world might depend on alternate sources for secure interrupts (secure timer or platform timer) instead of non-secure timers, in which case this save and restore is unnecessary. This patch introduces a boolean build-time configuration NS_TIMER_SWITCH to choose whether or not to save and restore non-secure timer registers upon world switch. The default choice is made not to save and restore them. Fixes ARM-software/tf-issues#148 Change-Id: I1b9d623606acb9797c3e0b02fb5ec7c0a414f37e
2014-05-16Document summary of build options in user guideJeenu Viswambharan
Change-Id: I6bd077955bf3780168a874705974bbe72ea0f5f1
2014-04-24FVP secure memory support documentationHarry Liebel
Fixes ARM-software/tf-issues#64 Change-Id: I4e56c25f9dc7f486fbf6fa2f7d8253874119b989
2014-03-05Enable platforms to omit some bootloadersJon Medhurst
If a platform doesn't specify a BLx_SOURCE variable, then building of the corresponding bootloader isn't attempted. Also allow BL3-3 to be omitted from the FIP. Note, this change also removes support for PLAT=all and the 'fip' target from the 'all' recipe. Fixes ARM-software/tf-issues#30 Change-Id: Ibdfead0440256eaf364617ecff65290ca6fe6240 Signed-off-by: Jon Medhurst <tixy@linaro.org>
2014-02-28Separate firmware design out of user-guide.mdDan Handley
Move the firmware design documentation out of user-guide.md and into a new file - firmware-design.md. Reformat the section headers. Change-Id: I664815dd47011c7c1cf2202aa4472a8fd78ebb92
2014-02-28Update versions of dependencies in user-guide.mdDan Handley
1. Update user-guide.md with the latest versions of dependent components required by the tested configurations of ARM Trusted Firmware. This includes the tested versions of Fixed Virtual Platforms (FVPs), toolchain, EFI Development Kit 2(EDK2), Linux kernel and Linux file system. 2. Remove the instructions to configure the Cortex Base FVP with the legacy GICv2 memory map as this is no longer supported since version 5.3 of the Base FVPs. 3. General tidyup of "Using the software" section. Change-Id: If8264cd29036b59dc5ff435b5f8b1d072dd36ef0
2014-02-20Add support for BL3-2 in BL3-1Achin Gupta
This patch adds the following support to the BL3-1 stage: 1. BL3-1 allows runtime services to specify and determine the security state of the next image after BL3-1. This has been done by adding the `bl31_set_next_image_type()` & `bl31_get_next_image_type()` apis. The default security state is non-secure. The platform api `bl31_get_next_image_info()` has been modified to let the platform decide which is the next image in the desired security state. 2. BL3-1 exports the `bl31_prepare_next_image_entry()` function to program entry into the target security state. It uses the apis introduced in 1. to do so. 3. BL3-1 reads the information populated by BL2 about the BL3-2 image into its internal data structures. 4. BL3-1 introduces a weakly defined reference `bl32_init()` to allow initialisation of a BL3-2 image. A runtime service like the Secure payload dispatcher will define this function if present. Change-Id: Icc46dcdb9e475ce6575dd3f9a5dc7a48a83d21d1
2014-02-20Add support for BL3-2 in BL2Achin Gupta
This patch adds support for loading a BL3-2 image in BL2. In case a BL3-2 image is found, it also passes information to BL3-1 about where it is located and the extents of memory available to it. Information about memory extents is populated by platform specific code. The documentation has also been updated to reflect the above changes. Change-Id: I526b2efb80babebab1318f2b02e319a86d6758b0 Co-authored-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2014-02-20Rework BL2 to BL3-1 hand over interfaceAchin Gupta
This patch reworks BL2 to BL3-1 hand over interface by introducing a composite structure (bl31_args) that holds the superset of information that needs to be passed from BL2 to BL3-1. - The extents of secure memory available to BL3-1 - The extents of memory available to BL3-2 (not yet implemented) and BL3-3 - Information to execute BL3-2 (not yet implemented) and BL3-3 images This patch also introduces a new platform API (bl2_get_bl31_args_ptr) that needs to be implemented by the platform code to export reference to bl31_args structure which has been allocated in platform-defined memory. The platform will initialize the extents of memory available to BL3-3 during early platform setup in bl31_args structure. This obviates the need for bl2_get_ns_mem_layout platform API. BL2 calls the bl2_get_bl31_args_ptr function to get a reference to bl31_args structure. It uses the 'bl33_meminfo' field of this structure to load the BL3-3 image. It sets the entry point information for the BL3-3 image in the 'bl33_image_info' field of this structure. The reference to this structure is passed to the BL3-1 image. Also fixes issue ARM-software/tf-issues#25 Change-Id: Ic36426196dd5ebf89e60ff42643bed01b3500517
2014-02-17Add Firmware Image Package (FIP) documentationHarry Liebel
This fixes ARM-software/tf-issues#9 Change-Id: Id57037115b8762efc9eaf5ff41887b71d6494c5d
2014-01-30Allow style checking of tree and local changesIan Spray
New phony Makefile targets have been added: * checkcodebase * checkpatch The checkcodebase target will run a Linux style compliance check over the entire codebase, and honours the V=1 Makefile verbose setting and so will show more information when this is enabled. If the local directory is a git checkout then the output of git ls-files is used to decide which files to test for compliance. If the local directory is not under git control then a 'best attempt' is made, but in this case it should be noted that it is possible for additional non-codebase files to be tested, so care should be taken when parsing the output. The checkpatch target will compare local changes against the git origin/master to allow issues with the last set of changes to be identified. To override the change comparision location, set the BASE_COMMIT variable to your desired git branch. Both targets rely on the Linux source tree script checkpatch.pl to do the syntax checking, and expects that the CHECKPATCH environment variable points to the location of this file. Notes on the usage of these targets have been added to the contributing.md and docs/user-guide.md text files. Change-Id: I6d73c97af578e24a34226d972afadab9d30f1d8d
2014-01-20Build system: Fixes #2: Add multi-platform supportRyan Harkin
Move all explicit platform or architecture specific references into a new platform.mk file that is defined for each platform. Change-Id: I9d6320d1ba957e0cc8d9b316b3578132331fa428 Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
2014-01-17Do not trap access to floating point registersHarry Liebel
Traps when accessing architectural features are disabled by clearing bits in CPTR_EL3 during early boot, including accesses to floating point registers. The value of this register was previously undetermined, causing unwanted traps to EL3. Future EL3 code (for example, context save/restore code) may use floating point registers, although they are not used by current code. Also, the '-mgeneral-regs-only' flag is enabled in the GCC settings to prevent generation of code that uses floating point registers. Change-Id: I9a03675f6387bbbee81a6f2c9ccf81150db03747
2014-01-17Update year in copyright text to 2014Dan Handley
Change-Id: Ic7fb61aabae1d515b9e6baf3dd003807ff42da60
2013-12-05psci: update docs with status of cpu_suspend apiAchin Gupta
This patch makes changes to the documents to reflect the current state of play of the psci cpu_suspend function. Change-Id: I086509fb75111b6e9f93b7f6dbcd33cc4591b9f3
2013-12-05Enable third party contributionsDan Handley
- Add instructions for contributing to ARM Trusted Firmware. - Update copyright text in all files to acknowledge contributors. Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
2013-12-05Update user guide further to linker scripts changesSandrine Bailleux
This patch updates the user guide section about the memory layout. - Explain the verifications that the linker scripts does on the global memory layout. - Refer to the new linker symbols. - Describe the linker symbols exported to the trusted firmware code. Change-Id: I033ab2b867e8b9776deb4185b9986bcb8218f286
2013-11-27Generate build products in sub-directoriesJames Morrissey
A single binary can be compiled using a command such as: make CROSS_COMPILE=aarch64-none-elf- bl1 Also make use of brackets consistent in the Makefile. Change-Id: I2180fdb473411ef7cffe39670a7b2de82def812e
2013-11-27Increase default amount of RAM for Base FVPs in FDTsHarry Liebel
- Large RAM-disks may have trouble starting with 2GB of memory. - Increase from 2GB to 4GB in FDT. Change-Id: I12c1b8e5db41114b88c69c48621cb21247a6a6a7
2013-11-27Unmask SError and Debug exceptions.Sandrine Bailleux
Any asynchronous exception caused by the firmware should be handled in the firmware itself. For this reason, unmask SError exceptions (and Debug ones as well) on all boot paths. Also route external abort and SError interrupts to EL3, otherwise they will target EL1. Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092
2013-11-14Fix documentation issues in v0.2 releaseJames Morrissey
Change-Id: I4e2a9daa97e3be3d2f53894f2ec7947ba6bb3a16
2013-11-14Add Foundation FVP documentationHarry Liebel
Change-Id: I5e47ba96e128d3a793517441f5a6c9f2ccbdfc66
2013-10-25ARMv8 Trusted Firmware release v0.2v0.2Achin Gupta