AgeCommit message (Collapse)Author
2014-06-26Merge pull request #154 from athoelke/at/inline-mmioHEADmasterAndrew Thoelke
Inline the mmio accessor functions
2014-06-26Merge pull request #153 from athoelke/at/remove-psci-mpidrAndrew Thoelke
Remove current CPU mpidr from PSCI common code
2014-06-25Remove current CPU mpidr from PSCI common codeAndrew Thoelke
Many of the interfaces internal to PSCI pass the current CPU MPIDR_EL1 value from function to function. This is not required, and with inline access to the system registers is less efficient than requiring the code to read that register whenever required. This patch remove the mpidr parameter from the affected interfaces and reduces code in FVP BL3-1 size by 160 bytes. Change-Id: I16120a7c6944de37232016d7e109976540775602
2014-06-24Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2danh-arm
Remove all checkpatch errors from codebase
2014-06-24Merge pull request #150 from sandrine-bailleux/sb/fix-plat-print-gic-regsdanh-arm
fvp: Fix register name in 'plat_print_gic_regs' macro
2014-06-24Merge pull request #149 from sandrine-bailleux/sb/warn-missing-include-dirsdanh-arm
Compile with '-Wmissing-include-dirs' flag
2014-06-24Merge pull request #147 from athoelke/at/remove-bakery-mpidrdanh-arm
Remove calling CPU mpidr from bakery lock API
2014-06-24Inline the mmio accessor functionsAndrew Thoelke
Making the simple mmio_read_*() and mmio_write_*() functions inline saves 360 bytes of code in FVP release build. Fixes ARM-software/tf-issues#210 Change-Id: I65134f9069f3b2d8821d882daaa5fdfe16355e2f
2014-06-24Remove all checkpatch errors from codebaseJuan Castillo
Exclude stdlib files because they do not follow kernel code style. Fixes ARM-software/tf-issues#73 Change-Id: I4cfafa38ab436f5ab22c277cb38f884346a267ab
2014-06-24fvp: Fix register name in 'plat_print_gic_regs' macroSandrine Bailleux
The 'plat_print_gic_regs' macro was accessing the GICC_CTLR register using the GICD_CTLR offset. This still generates the right code in the end because GICD_CTLR == GICC_CTLR but this patch fixes it for the logic of the code. Change-Id: I7b17af50e587f07bec0e4c933e346088470c96f3
2014-06-23Remove calling CPU mpidr from bakery lock APIAndrew Thoelke
The bakery lock code currently expects the calling code to pass the MPIDR_EL1 of the current CPU. This is not always done correctly. Also the change to provide inline access to system registers makes it more efficient for the bakery lock code to obtain the MPIDR_EL1 directly. This change removes the mpidr parameter from the bakery lock interface, and results in a code reduction of 160 bytes for the ARM FVP port. Fixes ARM-software/tf-issues#213 Change-Id: I7ec7bd117bcc9794a0d948990fcf3336a367d543
2014-06-23Merge pull request #145 from athoelke/at/psci-memory-optimization-v2danh-arm
PSCI memory optimizations (v2)
2014-06-23Merge pull request #144 from athoelke/at/init-context-v2danh-arm
Initialise CPU contexts from entry_point_info (v2)
2014-06-23Correctly dimension the PSCI aff_map_node arrayAndrew Thoelke
The array of affinity nodes is currently allocated for 32 entries with the PSCI_NUM_AFFS value defined in psci.h. This is not enough for large systems, and will substantially over allocate the array for small systems. This patch introduces an optional platform definition PLATFORM_NUM_AFFS to platform_def.h. If defined this value is used for PSCI_NUM_AFFS, otherwise a value of two times the number of CPU cores is used. The FVP port defines PLATFORM_NUM_AFFS to be 10 which saves nearly 1.5KB of memory. Fixes ARM-software/tf-issues#192 Change-Id: I68e30ac950de88cfbd02982ba882a18fb69c1445
2014-06-23Eliminate psci_suspend_context arrayAndrew Thoelke
psci_suspend_context is an array of cache-line aligned structures containing the single power_state integer per cpu. This array is the only structure indexed by the aff_map_node.data integer. This patch saves 2KB of BL3-1 memory by placing the CPU power_state value directly in the aff_map_node structure. As a result, this value is now never cached and the cache clean when writing the value is no longer required. Fixes ARM-software/tf-issues#195 Change-Id: Ib4c70c8f79eed295ea541e7827977a588a19ef9b
2014-06-23Initialise CPU contexts from entry_point_infoAndrew Thoelke
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI and SPDs into two functions: * The first uses entry_point_info to initialize the relevant cpu_context for first entry into a lower exception level on a CPU * The second populates the EL1 and EL2 system registers as needed from the cpu_context to ensure correct entry into the lower EL This patch alters the way that BL3-1 determines which exception level is used when first entering EL1 or EL2 during cold boot - this is now fully determined by the SPSR value in the entry_point_info for BL3-3, as set up by the platform code in BL2 (or otherwise provided to BL3-1). In the situation that EL1 (or svc mode) is selected for a processor that supports EL2, the context management code will now configure all essential EL2 register state to ensure correct execution of EL1. This allows the platform code to run non-secure EL1 payloads directly without requiring a small EL2 stub or OS loader. Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
2014-06-23Merge pull request #143 from athoelke/at/remove-nsramdanh-arm
Remove NSRAM from FVP memory map
2014-06-23Merge pull request #140 from athoelke/at/psci_smc_handlerdanh-arm
PSCI SMC handler improvements
2014-06-23Compile with '-Wmissing-include-dirs' flagSandrine Bailleux
Add the '-Wmissing-include-dirs' flag to the CFLAGS and ASFLAGS to make the build fail if the compiler or the assembler is given a nonexistant directory in the list of directories to be searched for header files. Also remove 'include/bl1' and 'include/bl2' directories from the search path for header files as they don't exist anymore. Change-Id: I2475b78ba8b7b448b9d0afaa9ad975257f638b89
2014-06-23Merge pull request #138 from athoelke/at/cpu-contextdanh-arm
Move CPU context pointers into cpu_data
2014-06-23Merge pull request #137 from athoelke/at/no-early-exceptionsdanh-arm
Remove early_exceptions from BL3-1
2014-06-23Merge pull request #136 from athoelke/at/cpu-datadanh-arm
Per-cpu data cache restructuring
2014-06-23Merge pull request #142 from athoelke/at/fix-console_putcdanh-arm
Remove broken assertion in console_putc()
2014-06-20Remove NSRAM from FVP memory mapAndrew Thoelke
This memory is not used by the FVP port and requires an additional 4KB translation table. This patch removes the entry from the memory map and reduces the number of allocated translation tables. Fixes ARM-software/tf-issues#196 Change-Id: I5b959e4fe92f5f892ed127c40dbe6c85eed3ed72
2014-06-20Remove broken assertion in console_putc()Andrew Thoelke
The assertion in console_putc() would trigger a recursion that exhausts the stack and eventually aborts. This patch replaces the assertion with an error return if the console has not been initialized yet. Fixes ARM-software/tf-issues#208 Change-Id: I95f736ff215d69655eb5ba7ceac70dc1409d986a
2014-06-18Merge pull request #135 from soby-mathew/sm/remove-reinit-of-timersdanh-arm
Remove re-initialisation of system timers after warm boot for FVP
2014-06-18Remove re-initialisation of system timers after warm boot for FVPSoby Mathew
This patch removes the reinitialisation of memory mapped system timer registers after a warm boot for the FVP. The system timers in FVP are in the 'Always ON' power domain which meant the reinitialisation was redundant and it could have conflicted with the setup the normal world has done. The programming of CNTACR(x) and CNTNSAR, the system timer registers, are removed from the warm boot path with this patch. Fixes ARM-software/tf-issues#169 Change-Id: Ie982eb03d1836b15ef3cf1568de2ea68a08b443e
2014-06-17Merge pull request #134 from jcastillo-arm/jc/tf-issues/179danh-arm
Set correct value for SYS_ID_REV_SHIFT in FVP
2014-06-17Remove early_exceptions from BL3-1Andrew Thoelke
The crash reporting support and early initialisation of the cpu_data allow the runtime_exception vectors to be used from the start in BL3-1, removing the need for the additional early_exception vectors and 2KB of code from BL3-1. Change-Id: I5f8997dabbaafd8935a7455910b7db174a25d871
2014-06-16Move CPU context pointers into cpu_dataAndrew Thoelke
Moving the context pointers for each CPU into the per-cpu data allows for much more efficient access to the contexts for the current CPU. Change-Id: Id784e210d63cbdcddb44ac1591617ce668dbc29f
2014-06-16Per-cpu data cache restructuringAndrew Thoelke
This patch prepares the per-cpu pointer cache for wider use by: * renaming the structure to cpu_data and placing in new header * providing accessors for this CPU, or other CPUs * splitting the initialization of the TPIDR pointer from the initialization of the cpu_data content * moving the crash stack initialization to a crash stack function * setting the TPIDR pointer very early during boot Change-Id: Icef9004ff88f8eb241d48c14be3158087d7e49a3
2014-06-16Set correct value for SYS_ID_REV_SHIFT in FVPJuan Castillo
According to documentation, the Rev field is located at bit 28 in the V2M sysid register. Fixes ARM-software/tf-issues#179 Change-Id: I2abb7bdc092ccd3f41f8962dc8d8d8e44e8dfdc3
2014-06-16Merge pull request #133 from athoelke/at/crash-reporting-optdanh-arm
Make the BL3-1 crash reporting optional
2014-06-16Merge pull request #131 from athoelke/at/cm_get_contextdanh-arm
Provide cm_get/set_context() for current CPU
2014-06-16Merge pull request #130 from athoelke/at/inline-asm-sysreg-v2danh-arm
Make system register functions inline assembly v2
2014-06-16Merge pull request #128 from sandrine-bailleux/sb/make-load_image-ep-optionaldanh-arm
Make the entry point argument optional in load_image()
2014-06-12Merge pull request #127 from sandrine-bailleux/sb/fix-pl011-fifo-pollingachingupta
PL011: Fix a bug in the UART FIFO polling
2014-06-12Merge pull request #126 from sandrine-bailleux/sb/include-missing-hfileachingupta
Include 'platform_def.h' header file in 'crash_reporting.S'
2014-06-12Merge pull request #125 from sandrine-bailleux/sb/remove-bl2_el_change_mem_ptrachingupta
fvp: Remove unused 'bl2_el_change_mem_ptr' variable
2014-06-11Make the BL3-1 crash reporting optionalAndrew Thoelke
This patch makes the console crash dump of processor register state optional based on the CRASH_REPORTING make variable. This defaults to only being enabled for DEBUG builds. This can be overridden by setting a different value in the platform makefile or on the make command line. Change-Id: Icfa1b2d7ff0145cf0a85e8ad732f9cee7e7e993f
2014-06-11Provide cm_get/set_context() for current CPUAndrew Thoelke
All callers of cm_get_context() pass the calling CPU MPIDR to the function. Providing a specialised version for the current CPU results in a reduction in code size and better readability. The current function has been renamed to cm_get_context_by_mpidr() and the existing name is now used for the current-CPU version. The same treatment has been done to cm_set_context(), although only both forms are used at present in the PSCI and TSPD code. Change-Id: I91cb0c2f7bfcb950a045dbd9ff7595751c0c0ffb
2014-06-10Merge Pull Request #120 (patch 1) from 'linmaonly:lin_patch2'Andrew Thoelke
2014-06-10PSCI SMC handler improvementsAndrew Thoelke
The SMC handler for PSCI was not correctly handling calls from secure states, or from AArch32. This patch completes the handler implementation to correctly detect secure callers and to clear the top bits in parameters from AArch32 callers. The patch also reorganises the switch statement to separate SMC64 and SMC32 function IDs which allows the compiler to generate much smaller code for the function. Change-Id: I36b1ac81fb14253d257255d0477771d54fab0d11
2014-06-10Make system register functions inline assemblyAndrew Thoelke
Replace the current out-of-line assembler implementations of the system register and system instruction operations with inline assembler. This enables better compiler optimisation and code generation when accessing system registers. Fixes ARM-software/tf-issues#91 Change-Id: I149af3a94e1e5e5140a3e44b9abfc37ba2324476
2014-06-05fvp: Remove unused 'bl2_el_change_mem_ptr' variableSandrine Bailleux
'bl2_el_change_mem_ptr' variable is a left over from the former BL2/BL3-1 interface. Change-Id: Ib0979c8e2809e103a41f9c5cc4afec7dd21ac9ab
2014-06-05Make the entry point argument optional in load_image()Sandrine Bailleux
There are cases where the entry point information is useless to the caller, e.g. when an image just needs to be loaded in memory but won't ever be executed. This patch allows load_image() function to take a NULL pointer as the entry point argument. In this case, it won't be populated. Change-Id: Ie9394b054457706c6699926c5e0206e0c3851c56
2014-06-05PL011: Fix a bug in the UART FIFO pollingSandrine Bailleux
Before attempting to write a character, the PL011 driver polls the PL011_UARTFR_TXFF bit to know whether the UART FIFO is full. However, the comparison with 1 was incorrect because PL011_UARTFR_TXFF is not at bit 0. This patch fixes it. Change-Id: If78892345bbdc8a5e4ae4a1b7159753c609681b0
2014-06-05Include 'platform_def.h' header file in 'crash_reporting.S'Sandrine Bailleux
'crash_reporting.S' needs to include 'platform_def.h' to get the definition of PLATFORM_CORE_COUNT. Note: On FVP it was compiling because 'platform_def.h' gets included through 'plat/fvp/include/plat_macros.S' but we don't want to rely on that for other platforms. Change-Id: I51e974776dd0f3bda10ad9849f5ef7b30c629833
2014-06-03Merge pull request #122 from 'danh-arm:dh/v0.4-docs'Dan Handley
2014-06-03Merge pull request #124 from 'danh-arm:sm/imf-documentation'Dan Handley