AgeCommit message (Collapse)Author
2014-06-03Document design of the Interrupt Mangement FrameworkAchin Gupta
This patch adds documentation that describes the design of the Interrupt management framework in the ARM Trusted Firmware. The porting-guide.md has also been updated to describe the interface that should be implemented by each platform to support this framework. Change-Id: I3eda48e5c9456e6a9516956bee16a29e366633b7 Co-Authored-By: Soby Mathew <soby.mathew@arm.com>
2014-06-03Merge pull request #119 from 'soby-mathew:sm/doc_crash_reporting'Dan Handley
2014-06-03Merge pull request #117 from 'danh-arm:dh/v0.4-user-guide'Dan Handley
2014-06-03Merge pull request #121 'vikramkanigiri:vk/doc_for_133'Dan Handley
2014-06-03Documentation for BL3-1 hardening and reset vectorVikram Kanigiri
Update documentation with BL3-1 hardening interface changes and for using BL3-1 as a reset vector feature Change-Id: Iafdd05e7a8e66503409f2acc934372efef5bc51b
2014-06-03Trusted Firmware v0.4 release documentationDan Handley
Updates to readme.md and change-log.md to describe the features and changes in the v0.4 release. Change-Id: Ice0a7cf7abae349f552e662eac638a46acc5db3f
2014-06-03User guide updates for v0.4 releaseDan Handley
Update the Linux kernel, Linaro file system, FVP and DS-5 versions used for the v0.4 release in user-guide.md. Change-Id: I2265fc17c229d4b8cc52165d6583a4a579cdcee3
2014-06-02Enable mapping higher physical addressLin Ma
Current ATF uses a direct physical-to-virtual mapping, that is, a physical address is mapped to the same address in the virtual space. For example, physical address 0x8000_0000 is mapped to 0x8000_0000 virtual. This approach works fine for FVP as all its physical addresses fall into 0 to 4GB range. But for other platform where all I/O addresses are 48-bit long, If we follow the same direct mapping, we would need virtual address range from 0 to 0x8fff_ffff_ffff, which is about 144TB. This requires a significant amount of memory for MMU tables and it is not necessary to use that much virtual space in ATF. The patch is to enable mapping a physical address range to an arbitrary virtual address range (instead of flat mapping) Changed "base" to "base_va" and added "base_pa" in mmap_region_t and modified functions such as mmap_add_region and init_xlation_table etc. Fixes ARM-software/tf-issues#158
2014-06-02Documentation for the new crash reporting implementationSoby Mathew
This patch modifies and adds to the existing documentation for the crash reporting implementation in BL3-1. Change-Id: I2cfbfeeeb64996ec7d19a9ddf95295482899b4bd
2014-05-30Merge pull request #116 from 'danh-arm:dh/refactoring-docs'Dan Handley
2014-05-30Fix porting guide references to platform.hDan Handley
Following recent refactoring changes to platform.h, this commit updates porting-guide.md to correctly refer to platform.h and platform_def.h where appropriate. Change-Id: Idf1e77503c24358696f8f3c14caa0cc1d579deb4
2014-05-29Merge pull request #111 'soby-mathew-sm:fix_cookie_to_int_handler'Dan Handley
2014-05-29Merge pull request #115 'athoelke-at:fix-bl31-X1-parameter'Dan Handley
2014-05-29Merge pull request #114 from 'vikramkanigiri:vk/pass_bl33_args'Dan Handley
2014-05-29Fix compilation issue for IMF_READ_INTERRUPT_ID build flagSoby Mathew
This patch fixes the compilation issue for trusted firmware when the IMF_READ_INTERRUPT_ID is enabled. Change-Id: I94ab613b9bc96a7c1935796c674dc42246aaafee
2014-05-29Pass 'cookie' parameter to interrupt handler in BL3-1Soby Mathew
The interrupt handling routine in BL3-1 expects a cookie as its last parameter which was not being passed when invoking the interrupt handler in BL3-1. This patch fixes that by passing a dummy cookie parameter in the x3 register. Fixes ARM-software/tf-issues#171 Change-Id: Ic98abbbd9f849e6f1c55343e865b5e0a4904a1c5
2014-05-29Allow platform parameter X1 to be passed to BL3-1Andrew Thoelke
bl2_main() was overwriting any platform set X1 parameter for BL3-1 with the value zero. This patch ensure that any platform set value is correctly passed to BL3-1. The FVP port adds a check to verify this parameter is being passed correctly. Fixes ARM-software/tf-issues#173 Change-Id: Ifbcda73d3d41d2b04a4baf5614e9d2d21f1717c8
2014-05-28Pass the args to the BL3-3 entrypointVikram Kanigiri
At present the arguments for BL3-3 in the entry_point_info structure are not being transferred to X0-X7 before starting execution of this image This patch saves the args for BL3-3 into cpu context used for its entry Fixes ARM-software/tf-issues#172 Change-Id: I001b4b9bff6a264336f0d01d377619ae719f928b
2014-05-27Merge pull request #110 from soby-mathew:sm/support_normal_irq_in_tsp-v4 ↵Dan Handley
into for-v0.4
2014-05-27Merge pull request #112 from danh-arm:dh/refactor-plat-header-v4 into for-v0.4Dan Handley
2014-05-27Further renames of platform porting functionsDan Handley
Rename the ic_* platform porting functions to plat_ic_* to be consistent with the other functions in platform.h. Also rename bl31_get_next_image_info() to bl31_plat_get_next_image_ep_info() and remove the duplicate declaration in bl31.h. Change-Id: I4851842069d3cff14c0a468daacc0a891a7ede84
2014-05-27Remove FVP specific comments in platform.hDan Handley
Remove the FVP specific comments in platform.h since this file is re-usable across all platforms. Change-Id: Ifd4a4f72562adb3ecf8b9078b0150f170ef22dba
2014-05-27Fixup Standard SMC Resume HandlingSoby Mathew
This patch fixes a missed return and code alignment issues in TSP_FID_RESUME handling. Change-Id: Icf8aeb76dfd6898745653ce039e3bac45e0a9b3a
2014-05-23Add enable mmu platform porting interfacesDan Handley
Previously, the enable_mmu_elX() functions were implicitly part of the platform porting layer since they were included by generic code. These functions have been placed behind 2 new platform functions, bl31_plat_enable_mmu() and bl32_plat_enable_mmu(). These are weakly defined so that they can be optionally overridden by platform ports. Also, the enable_mmu_elX() functions have been moved to lib/aarch64/xlat_tables.c for optional re-use by platform ports. These functions are tightly coupled with the translation table initialization code. Fixes ARM-software/tf-issues#152 Change-Id: I0a2251ce76acfa3c27541f832a9efaa49135cc1c
2014-05-23Rename FVP specific files and functionsDan Handley
FVP specific files and functions containing the word "plat" have been renamed to use the word "fvp" to distinguish them from the common platform functionality and porting functions. Change-Id: I39f9673dab3ee9c74bd18b3e62b7c21027232f7d
2014-05-23Move BL porting functions into platform.hDan Handley
Some platform porting functions were in BL specific header files. These have been moved to platform.h so that all porting functions are in the same place. The functions are now grouped by BL. Obsolete BL headers files have been removed. Also, the weak declaration of the init_bl2_mem_layout() function has been moved out the header file and into the source file (bl_common.c) using the more succinct #pragma syntax. This mitigates the risk of 2 weak definitions being created and the wrong one being picked up by the compiler. Change-Id: Ib19934939fd755f3e5a5a5bceec88da684308a83
2014-05-23Split platform.h into separate headersDan Handley
Previously, platform.h contained many declarations and definitions used for different purposes. This file has been split so that: * Platform definitions used by common code that must be defined by the platform are now in platform_def.h. The exact include path is exported through $PLAT_INCLUDES in the platform makefile. * Platform definitions specific to the FVP platform are now in /plat/fvp/fvp_def.h. * Platform API declarations specific to the FVP platform are now in /plat/fvp/fvp_private.h. * The remaining platform API declarations that must be ported by each platform are still in platform.h but this file has been moved to /include/plat/common since this can be shared by all platforms. Change-Id: Ieb3bb22fbab3ee8027413c6b39a783534aee474a
2014-05-23Remove unused data declarationsDan Handley
Some data variables were declared but not used. These have been removed. Change-Id: I038632af3c32d88984cd25b886c43ff763269bf9
2014-05-23Remove extern keyword from function declarationsDan Handley
Function declarations implicitly have external linkage so do not need the extern keyword. Change-Id: Ia0549786796d8bf5956487e8996450a0b3d79f32
2014-05-23Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2Andrew Thoelke
2014-05-23doc: Update information about the memory layoutSandrine Bailleux
Rework the "Memory layout on FVP platforms" section in the Firmware Design document. Add information about where the TSP image fits in the memory layout when present. Add documentation for the base addresses of each bootloader image in the porting guide. Change-Id: I4afb2605e008a1cb28c44a697804f2cb6bb4c9aa
2014-05-23Make the memory layout more flexibleSandrine Bailleux
Currently the platform code gets to define the base address of each boot loader image. However, the linker scripts couteract this flexibility by enforcing a fixed overall layout of the different images. For example, they require that the BL3-1 image sits below the BL2 image. Choosing BL3-1 and BL2 base addresses in such a way that it violates this constraint makes the build fail at link-time. This patch requires the platform code to now define a limit address for each image. The linker scripts check that the image fits within these bounds so they don't rely anymore on the position of a given image in regard to the others. Fixes ARM-software/tf-issues#163 Change-Id: I8c108646825da19a6a8dfb091b613e1dd4ae133c
2014-05-23Make BL1 RO and RW base addresses configurableSandrine Bailleux
BL1 RO and RW base address used to be fixed, respectively to the first address of the Trusted ROM and the first address of the Trusted RAM. Introduce new platform defines to configure the BL1 RO and RW base addresses. Change-Id: If26616513a47798593a4bb845a4b0fb37c867cd6
2014-05-23Merge pull request #104 from athoelke:at/tsp-entrypoints-v2Andrew Thoelke
2014-05-23Merge pull request #105 from athoelke:sm/support_normal_irq_in_tsp-v2Andrew Thoelke
2014-05-23Merge pull request #102 from achingupta:ag/tf-issues#104-v2Andrew Thoelke
2014-05-23Merge pull request #100 from jcastillo-arm:jc/tf-issues/149-v4Andrew Thoelke
2014-05-23Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2Andrew Thoelke
2014-05-23Merge pull request #103 from athoelke:dh/tf-issues#68-v3Andrew Thoelke
2014-05-23Merge pull request #99 from vikramkanigiri:vk/tf-issues-133_V3Andrew Thoelke
2014-05-23Merge pull request #67 from achingupta:ag/psci_standby_bug_fixAndrew Thoelke
2014-05-23Limit BL3-1 read/write access to SRAMAndrew Thoelke
At present BL3-1 has access to all of the SRAM, including regions that are mapped as read-only and non-cacheable by other firmware images. This patch restricts BL3-1 to only be able to read/write from memory used for its own data sections Change-Id: I26cda1b9ba803d91a9eacda768f3ce7032c6db94 Conflicts: plat/fvp/bl31_plat_setup.c
2014-05-23Use a vector table for TSP entrypointsAndrew Thoelke
The TSP has a number of entrypoints used by the TSP on different occasions. These were provided to the TSPD as a table of function pointers, and required the TSPD to read the entry in the table, which is in TSP memory, in order to program the exception return address. Ideally, the TSPD has no access to the TSP memory. This patch changes the table of function pointers into a vector table of single instruction entrypoints. This allows the TSPD to calculate the entrypoint address instead of read it. Fixes ARM-software/tf-issues#160 Change-Id: Iec6e055d537ade78a45799fbc6f43765a4725ad3
2014-05-23Non-Secure Interrupt support during Standard SMC processing in TSPSoby Mathew
Implements support for Non Secure Interrupts preempting the Standard SMC call in EL1. Whenever an IRQ is trapped in the Secure world we securely handover to the Normal world to process the interrupt. The normal world then issues "resume" smc call to resume the previous interrupted SMC call. Fixes ARM-software/tf-issues#105 Change-Id: I72b760617dee27438754cdfc9fe9bcf4cc024858
2014-05-22Allow BL3-2 platform definitions to be optionalDan Handley
The generic image loading and IO FIP code no longer forces the platform to create BL3-2 (Secure-EL1 Payload) specific definitions. The BL3-2 loading code in bl2/bl2main.c is wrapped by a #ifdef BL32_BASE blocks, allowing the BL3-2 definitions to be optional. Similarly for the name_uuid array defintion in drivers/io/io_fip.c. Also update the porting guide to reflect this change. The BL3-2 platform definitions remain non-configurably present in the FVP port. Fixes ARM-software/tf-issues#68 Change-Id: Iea28b4e94d87a31f5522f271e290919a8a955460
2014-05-22Enable secure timer to generate S-EL1 interruptsAchin Gupta
This patch enables secure physical timer during TSP initialisation and maintains it across power management operations so that a timer interrupt is generated every half second. Fixes ARM-software/tf-issues#104 Fixes ARM-software/tf-issues#134 Change-Id: I66c6cfd24bd5e6035ba75ebf0f047e568770a369
2014-05-22Add S-EL1 interrupt handling support in the TSPDAchin Gupta
This patch adds support in the TSPD for registering a handler for S-EL1 interrupts. This handler ferries the interrupts generated in the non-secure state to the TSP at 'tsp_fiq_entry'. Support has been added to the smc handler to resume execution in the non-secure state once interrupt handling has been completed by the TSP. There is also support for resuming execution in the normal world if the TSP receives a EL3 interrupt. This code is currently unused. Change-Id: I816732595a2635e299572965179f11aa0bf93b69
2014-05-22Add support for asynchronous FIQ handling in TSPAchin Gupta
This patch adds support in the TSP to handle FIQ interrupts that are generated when execution is in the TSP. S-EL1 interrupt are handled normally and execution resumes at the instruction where the exception was originally taken. S-EL3 interrupts i.e. any interrupt not recognized by the TSP are handed to the TSPD. Execution resumes normally once such an interrupt has been handled at EL3. Change-Id: Ia3ada9a4fb15670afcc12538a6456f21efe58a8f
2014-05-22Add support for synchronous FIQ handling in TSPAchin Gupta
This patch adds support in the TSP for handling S-EL1 interrupts handed over by the TSPD. It includes GIC support in its platform port, updates various statistics related to FIQ handling, exports an entry point that the TSPD can use to hand over interrupts and defines the handover protocol w.r.t what context is the TSP expected to preserve and the state in which the entry point is invoked by the TSPD. Change-Id: I93b22e5a8133400e4da366f5fc862f871038df39
2014-05-22Use secure timer to generate S-EL1 interruptsAchin Gupta
This patch adds support in the TSP to program the secure physical generic timer to generate a EL-1 interrupt every half second. It also adds support for maintaining the timer state across power management operations. The TSPD ensures that S-EL1 can access the timer by programming the SCR_EL3.ST bit. This patch does not actually enable the timer. This will be done in a subsequent patch once the complete framework for handling S-EL1 interrupts is in place. Change-Id: I1b3985cfb50262f60824be3a51c6314ce90571bc