AgeCommit message (Collapse)Author
2014-05-09Introduce IS_IN_ELX() macrosSandrine Bailleux
The goal of these macros is to improve code readability by providing a concise way to check whether we are running in the expected exception level. Change-Id: If9aebadfb6299a5196e9a582b442f0971d9909b1
2014-05-08Merge pull request #65 from vikramkanigiri/vk/console_initdanh-arm
Ensure a console is initialized before it is used
2014-05-08Merge pull request #63 from ↵danh-arm
soby-mathew/sm/save_callee_saved_registers_in_cpu_context-1 Preserve x19-x29 across world switch for exception handling
2014-05-08Ensure a console is initialized before it is usedVikram Kanigiri
This patch moves console_init() to bl32_early_platform_setup(). It also ensures that console_init() is called in each blX_early_platform_setup() function before the console is used e.g. through a printf call in an assert() statement. Fixes ARM-software/TF-issues#127 Change-Id: I5b1f17e0152bab674d807d2a95ff3689c5d4794e
2014-05-08Merge pull request #62 from athoelke/set-little-endian-v2danh-arm
Set processor endianness immediately after RESET v2
2014-05-08Preserve x19-x29 across world switch for exception handlingSoby Mathew
Previously exception handlers in BL3-1, X19-X29 were not saved and restored on every SMC/trap into EL3. Instead these registers were 'saved as needed' as a side effect of the A64 ABI used by the C compiler. That approach failed when world switching but was not visible with the TSP/TSPD code because the TSP is 64-bit, did not clobber these registers when running and did not support pre-emption by normal world interrupts. These scenarios showed that the values in these registers can be passed through a world switch, which broke the normal and trusted world assumptions about these registers being preserved. The Ideal solution saves and restores these registers when a world switch occurs - but that type of implementation is more complex. So this patch always saves and restores these registers on entry and exit of EL3. Fixes ARM-software/tf-issues#141 Change-Id: I9a727167bbc594454e81cf78a97ca899dfb11c27
2014-05-08Merge pull request #58 from athoelke/optimise-cache-flush-v2danh-arm
Optimise data cache clean/invalidate operation v2
2014-05-08Merge pull request #61 from athoelke/use-mrs-msr-from-assembler-v2danh-arm
Use MRS/MSR instructions in assembler code v2
2014-05-08Merge pull request #60 from athoelke/disable-mmu-v2danh-arm
Replace disable_mmu with assembler version v2
2014-05-08Merge pull request #59 from athoelke/review-barriers-v2danh-arm
Correct usage of data and instruction barriers v2
2014-05-08Merge pull request #57 from sandrine-bailleux/sb/remove-pl011-basedanh-arm
Remove unused 'PL011_BASE' macro
2014-05-08Remove unused 'PL011_BASE' macroSandrine Bailleux
'PL011_BASE' macro is no longer used because the right UART base address is now directly given to the 'console_init()' function. This patch removes it. Change-Id: I94759c99602df4876291a56f9f6a75de337a65ec
2014-05-07Optimise data cache clean/invalidate operationAndrew Thoelke
The data cache clean and invalidate operations dcsw_op_all() and dcsw_op_loius() were implemented to invoke a DSB and ISB barrier for every set/way operation. This adds a substantial performance penalty to an already expensive operation. These functions have been reworked to provide an optimised implementation derived from the code in section D3.4 of the ARMv8 ARM. The helper macro setup_dcsw_op_args has been moved and reworked alongside the implementation. Fixes ARM-software/tf-issues#146 Change-Id: Icd5df57816a83f0a842fce935320a369f7465c7f
2014-05-07Remove unused or invalid asm helper functionsAndrew Thoelke
There are a small number of non-EL specific helper functions which are no longer used, and also some unusable helper functions for non-existant registers. This change removes all of these functions. Change-Id: Idd656cef3b59cf5c46fe2be4029d72288b649c24
2014-05-07Access system registers directly in assemblerAndrew Thoelke
Instead of using the system register helper functions to read or write system registers, assembler coded functions should use MRS/MSR instructions. This results in faster and more compact code. This change replaces all usage of the helper functions with direct register accesses. Change-Id: I791d5f11f257010bb3e6a72c6c5ab8779f1982b3
2014-05-07Replace disable_mmu with assembler versionAndrew Thoelke
disable_mmu() cannot work as a C function as there is no control over data accesses generated by the compiler between disabling and cleaning the data cache. This results in reading stale data from main memory. As assembler version is provided for EL3, and a variant that also disables the instruction cache which is now used by the BL1 exception handling function. Fixes ARM-software/tf-issues#147 Change-Id: I0cf394d2579a125a23c2f2989c2e92ace6ddb1a6
2014-05-07Correct usage of data and instruction barriersAndrew Thoelke
The current code does not always use data and instruction barriers as required by the architecture and frequently uses barriers excessively due to their inclusion in all of the write_*() helper functions. Barriers should be used explicitly in assembler or C code when modifying processor state that requires the barriers in order to enable review of correctness of the code. This patch removes the barriers from the helper functions and introduces them as necessary elsewhere in the code. PORTING NOTE: check any port of Trusted Firmware for use of system register helper functions for reliance on the previous barrier behaviour and add explicit barriers as necessary. Fixes ARM-software/tf-issues#92 Change-Id: Ie63e187404ff10e0bdcb39292dd9066cb84c53bf
2014-05-07Set processor endianness immediately after RESETAndrew Thoelke
SCTLR_EL3.EE is being configured too late in bl1_arch_setup() and bl31_arch_setup() after data accesses have already occured on the cold and warm boot paths. This control bit must be configured immediately on CPU reset to match the endian state of the firmware (little endian). Fixes ARM-software/tf-issues#145 Change-Id: Ie12e46fbbed6baf024c30beb50751591bb8c8655
2014-05-06Merge pull request #49 from danh-arm/dh/remove-non-const-datadanh-arm
Remove variables from .data section
2014-05-06Remove variables from .data sectionDan Handley
Update code base to remove variables from the .data section, mainly by using const static data where possible and adding the const specifier as required. Most changes are to the IO subsystem, including the framework APIs. The FVP power management code is also affected. Delay initialization of the global static variable, next_image_type in bl31_main.c, until it is realy needed. Doing this moves the variable from the .data to the .bss section. Also review the IO interface for inconsistencies, using uintptr_t where possible instead of void *. Remove the io_handle and io_dev_handle typedefs, which were unnecessary, replacing instances with uintptr_t. Fixes ARM-software/tf-issues#107. Change-Id: I085a62197c82410b566e4698e5590063563ed304
2014-05-06Merge pull request #48 from danh-arm/dh/major-refactoringdanh-arm
dh/major refactoring
2014-05-06Reduce deep nesting of header filesDan Handley
Reduce the number of header files included from other header files as much as possible without splitting the files. Use forward declarations where possible. This allows removal of some unnecessary "#ifndef __ASSEMBLY__" statements. Also, review the .c and .S files for which header files really need including and reorder the #include statements alphabetically. Fixes ARM-software/tf-issues#31 Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
2014-05-06Always use named structs in header filesDan Handley
Add tag names to all unnamed structs in header files. This allows forward declaration of structs, which is necessary to reduce header file nesting (to be implemented in a subsequent commit). Also change the typedef names across the codebase to use the _t suffix to be more conformant with the Linux coding style. The coding style actually prefers us not to use typedefs at all but this is considered a step too far for Trusted Firmware. Also change the IO framework structs defintions to use typedef'd structs to be consistent with the rest of the codebase. Change-Id: I722b2c86fc0d92e4da3b15e5cab20373dd26786f
2014-05-06Move PSCI global functions out of private headerDan Handley
Move the PSCI global functions out of psci_private.h and into psci.h to allow the standard service to only depend on psci.h. Change-Id: I8306924a3814b46e70c1dcc12524c7aefe06eed1
2014-05-06Separate BL functions out of arch.hDan Handley
Move the BL function prototypes out of arch.h and into the appropriate header files to allow more efficient header file inclusion. Create new BL private header files where there is no sensible existing header file. Change-Id: I45f3e10b72b5d835254a6f25a5e47cf4cfb274c3
2014-05-06Refactor GIC header filesDan Handley
Move the function prototypes from gic.h into either gic_v2.h or gic_v3.h as appropriate. Update the source files to include the correct headers. Change-Id: I368cfda175cdcbd3a68f46e2332738ec49048e19
2014-05-06Separate out CASSERT macro into own headerDan Handley
Separate out the CASSERT macro out of bl_common.h into its own header to allow more efficient header inclusion. Change-Id: I291be0b6b8f9879645e839a8f0dd1ec9b3db9639
2014-05-06Remove vpath usage in makefilesDan Handley
Remove all usage of the vpath keyword in makefiles as it was prone to mistakes. Specify the relative paths to source files instead. Also reorder source files in makefiles alphabetically. Fixes ARM-software/tf-issues#121 Change-Id: Id15f60655444bae60e0e2165259efac71a50928b
2014-05-06Make use of user/system includes more consistentDan Handley
Make codebase consistent in its use of #include "" syntax for user includes and #include <> syntax for system includes. Fixes ARM-software/tf-issues#65 Change-Id: If2f7c4885173b1fd05ac2cde5f1c8a07000c7a33
2014-05-06Move FVP power driver to FVP platformDan Handley
Move the FVP power driver to a directory under the FVP platform port as this is not a generically usable driver. Change-Id: Ibc78bd88752eb3e3964336741488349ac345f4f0
2014-05-06Move include and source files to logical locationsDan Handley
Move almost all system include files to a logical sub-directory under ./include. The only remaining system include directories not under ./include are specific to the platform. Move the corresponding source files to match the include directory structure. Also remove pm.h as it is no longer used. Change-Id: Ie5ea6368ec5fad459f3e8a802ad129135527f0b3
2014-05-01Merge pull request #50 from vikramkanigiri/vk/tf-issues#26achingupta
Preserve PSCI cpu_suspend 'power_state' parameter.
2014-04-29Preserve PSCI cpu_suspend 'power_state' parameter.Vikram Kanigiri
This patch saves the 'power_state' parameter prior to suspending a cpu and invalidates it upon its resumption. The 'affinity level' and 'state id' fields of this parameter can be read using a set of public and private apis. Validation of power state parameter is introduced which checks for SBZ bits are zero. This change also takes care of flushing the parameter from the cache to main memory. This ensures that it is available after cpu reset when the caches and mmu are turned off. The earlier support for saving only the 'affinity level' field of the 'power_state' parameter has also been reworked. Fixes ARM-Software/tf-issues#26 Fixes ARM-Software/tf-issues#130 Change-Id: Ic007ccb5e39bf01e0b67390565d3b4be33f5960a
2014-04-24Merge pull request #33 from hliebel/hl/secure-memorydanh-arm
Hl/secure memory
2014-04-24FVP secure memory support documentationHarry Liebel
Fixes ARM-software/tf-issues#64 Change-Id: I4e56c25f9dc7f486fbf6fa2f7d8253874119b989
2014-04-24Enable secure memory support for FVPsHarry Liebel
- Use the TrustZone controller on Base FVP to program DRAM access permissions. By default no access to DRAM is allowed if 'secure memory' is enabled on the Base FVP. - The Foundation FVP does not have a TrustZone controller but instead has fixed access permissions. - Update FDTs for Linux to use timers at the correct security level. - Starting the FVPs with 'secure memory' disabled is also supported. Limitations: Virtio currently uses a reserved NSAID. This will be corrected in future FVP releases. Change-Id: I0b6c003a7b5982267815f62bcf6eb82aa4c50a31
2014-04-24Add TrustZone (TZC-400) driverHarry Liebel
The TZC-400 performs security checks on transactions to memory or peripherals. Separate regions can be created in the address space each with individual security settings. Limitations: This driver does not currently support raising an interrupt on access violation. Change-Id: Idf8ed64b4d8d218fc9b6f9d75acdb2cd441d2449
2014-04-22Merge pull request #43 from danh-arm/dh/tf-issues#129danh-arm
Move console.c to pl011 specific driver location
2014-04-22Merge pull request #44 from danh-arm/dh/tf-issues#136danh-arm
Remove redundant code from bl1_plat_helpers.S
2014-04-16Merge pull request #45 from danh-arm/dh/tf-issues#114danh-arm
Rename FVP "mmap" array to avoid name confusion
2014-04-16Remove redundant code from bl1_plat_helpers.SDan Handley
Remove redundant code in plat_secondary_cold_boot_setup() in plat/fvp/aarch64/bl1_plat_helpers.S. Fixes ARM-software/tf-issues#136 Change-Id: I98c0a46d95cfea33125e34e609c83dc2c97cd86e
2014-04-16Merge pull request #40 from athoelke/at/up-stacks-76-v2danh-arm
Allocate single stacks for BL1 and BL2 (v2)
2014-04-15Allocate single stacks for BL1 and BL2Andrew Thoelke
The BL images share common stack management code which provides one coherent and one cacheable stack for every CPU. BL1 and BL2 just execute on the primary CPU during boot and do not require the additional CPU stacks. This patch provides separate stack support code for UP and MP images, substantially reducing the RAM usage for BL1 and BL2 for the FVP platform. This patch also provides macros for declaring stacks and calculating stack base addresses to improve consistency where this has to be done in the firmware. The stack allocation source files are now included via platform.mk rather than the common BLx makefiles. This allows each platform to select the appropriate MP/UP stack support for each BL image. Each platform makefile must be updated when including this commit. Fixes ARM-software/tf-issues#76 Change-Id: Ia251f61b8148ffa73eae3f3711f57b1ffebfa632
2014-04-15Rename FVP "mmap" array to avoid name confusionDan Handley
Rename the array "mmap" in plat/fvp/aarch64/plat_common.c to "fvp_mmap", to avoid confusion with the array of the same name in lib/arch/aarch64/xlat_tables.c Fixes ARM-software/tf-issues#114 Change-Id: I61478c0070aa52d5dcf5d85af2f353f56c060cfb
2014-04-15Merge pull request #36 from athoelke/at/gc-sections-80danh-arm
Using GCC --gc-sections to eliminate unused code and data
2014-04-14Move console.c to pl011 specific driver locationDan Handley
Rename drivers/console/console.c to drivers/arm/peripherals/pl011/pl011_console.c. This makes it clear that this is a pl011 specific console implementation. Fixes ARM-software/tf-issues#129 Change-Id: Ie2f8109602134c5b86993e32452c70734c45a3ed
2014-04-11Merge pull request #38 from sandrine-bailleux/sb/tf-issue-125danh-arm
Fix system counter initialisation
2014-04-08Define frequency of system counter in platform codeSandrine Bailleux
BL3-1 architecture setup code programs the system counter frequency into the CNTFRQ_EL0 register. This frequency is defined by the platform, though. This patch introduces a new platform hook that the architecture setup code can call to retrieve this information. In the ARM FVP port, this returns the first entry of the frequency modes table from the memory mapped generic timer. All system counter setup code has been removed from BL1 as some platforms may not have initialized the system counters at this stage. The platform specific settings done exclusively in BL1 have been moved to BL3-1. In the ARM FVP port, this consists in enabling and initializing the System level generic timer. Also, the frequency change request in the counter control register has been set to 0 to make it explicit it's using the base frequency. The CNTCR_FCREQ() macro has been fixed in this context to give an entry number rather than a bitmask. In future, when support for firmware update is implemented, there is a case where BL1 platform specific code will need to program the counter frequency. This should be implemented at that time. This patch also updates the relevant documentation. It properly fixes ARM-software/tf-issues#24 Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
2014-04-08Revert "Move architecture timer setup to platform-specific code"Sandrine Bailleux
This reverts commit 1c297bf015226c182b66498d5a64b8b51c7624f5 because it introduced a bug: the CNTFRQ_EL0 register was no longer programmed by all CPUs. bl31_platform_setup() function is invoked only in the cold boot path and consequently only on the primary cpu. A subsequent commit will correctly implement the necessary changes to the counter frequency setup code. Fixes ARM-software/tf-issues#125 Conflicts: docs/firmware-design.md plat/fvp/bl31_plat_setup.c Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54
2014-04-07Merge pull request #35 from sandrine-bailleux/sb/add-missing-include-guarddanh-arm
Add missing #include guard in xlat_tables.h