AgeCommit message (Collapse)Author
2013-12-20Add strchr() and putchar() to local C libraryHarry Liebel
Change-Id: I3659e119a242f8ef828e32bfdf5d0b4b7ac4f716
2013-12-20Create local C library implementation (2/2)Harry Liebel
- This change is split into two separate patches in order to simplify the history as interpreted by 'git'. The split is between the move/rename and addition of new files. - Remove dependency on toolchain C library headers and functions in order to ensure behavioural compatibility between toolchains. - Use FreeBSD as reference for C library implementation. - Do not let GCC use default library include paths. - Remove unused definitions in modified headers and implementations. - Move C library files to 'lib/stdlib' and 'include/stdlib'. - Break std.c functions out into separate files. Change-Id: I3e3d8d992052264d2a02489034ae4c03bf0f5512
2013-12-20Create local C library implementation (1/2)Harry Liebel
- This change is split into two separate patches in order to simplify the history as interpreted by 'git'. The split is between the move/rename and addition of new files. - Remove dependency on toolchain C library headers and functions in order to ensure behavioural compatibility between toolchains. - Use FreeBSD as reference for C library implementation. - Do not let GCC use default library include paths. - Remove unused definitions in modified headers and implementations. - Move C library files to 'lib/stdlib' and 'include/stdlib'. - Break std.c functions out into separate files. Change-Id: I91cddfb3229775f770ad781589670c57d347a154
2013-12-20Add debug macrosHarry Liebel
- Add 'debug.h' with INFO, WARN and ERROR macros. - This prints the specified message with the appropriate tag. - INFO and WARN messages are only displayed when building with the DEBUG flag set. Error messages are always printed. Change-Id: I21835b6063fcc99649b30ac7489387cbd3705bc0
2013-12-12Make BL31's ns_entry_info a single-cpu areaSandrine Bailleux
ns_entry_info used to be a per-cpu array. This is a waste of space because it is only accessed by the primary CPU on the cold boot path. This patch reduces ns_entry_info to a single-cpu area. Change-Id: I647c70c4e76069560f1aaad37a1d5910f56fba4c
2013-12-12BL2: Sanity check value in x0 in the entry point codeSandrine Bailleux
Change-Id: Icef68e314e6ba0f3694189b57f4b1dbbea5ba255
2013-12-12Move RUN_IMAGE constant from bl1.h to bl_common.hSandrine Bailleux
RUN_IMAGE constant is used by all bootloader stages. Change-Id: I1b4e28d8fcf3ad1363f202c859f5efab0f320efe
2013-12-12Remove useless copies of meminfo structuresSandrine Bailleux
Platform setup code has to reserve some memory for storing the memory layout information. It is populated in early platform setup code. blx_get_sec_mem_layout() functions used to return a copy of this structure. This patch modifies blx_get_sec_mem_layout() functions so that they now directly return a pointer to their memory layout structure. It ensures that the memory layout returned by blx_get_sec_mem_layout() is always up-to-date and also avoids a useless copy of the meminfo structure. Also rename blx_get_sec_mem_layout() to blx_plat_sec_mem_layout() to make it clear those functions are platform specific. Change-Id: Ic7a6f9d6b6236b14865ab48a9f5eff545ce56551
2013-12-05psci: update docs with status of cpu_suspend apiAchin Gupta
This patch makes changes to the documents to reflect the current state of play of the psci cpu_suspend function. Change-Id: I086509fb75111b6e9f93b7f6dbcd33cc4591b9f3
2013-12-05psci: rectify and homogenise generic codeAchin Gupta
This patch performs a major rework of the psci generic implementation to achieve the following: 1. replace recursion with iteration where possible to aid code readability e.g. affinity instance states are changed iteratively instead of recursively. 2. acquire pointers to affinity instance nodes at the beginning of a psci operation. All subsequent actions use these pointers instead of calling psci_get_aff_map_node() repeatedly e.g. management of locks has been abstracted under functions which use these pointers to ensure correct ordering. Helper functions have been added to create these abstractions. 3. assertions have been added to cpu level handlers to ensure correct state transition 4. the affinity level extents specified to various functions have the same meaning i.e. start level is always less than the end level. Change-Id: If0508c3a7b20ea3ddda2a66128429382afc3dfc8
2013-12-05psci: rework cpu_off assertion and minor cleanupsAchin Gupta
This patch: 1. removes a duplicate assertion to check that the only error condition that can be returned while turning a cpu off is PSCI_E_DENIED. Having this assertion after calling psci_afflvl_off() is sufficient. 2. corrects some incorrect usage of 'its' vs 'it is' 3. removes some unwanted white spaces Change-Id: Icf014e269b54f5be5ce0b9fbe6b41258e4ebf403
2013-12-05remove check on non-secure entrypoint parameterAchin Gupta
In fvp_affinst_on/suspend, the non-secure entrypoint is always expected to lie in the DRAM. This check will not be valid if non-secure code executes directly out of flash e.g. a baremetal test. This patch removes this check. Change-Id: I0436e1138fc394aae8ff1ea59ebe38b46a440b61
2013-12-05move timer #defines & remove duplicate declarationAchin Gupta
This patch removes the duplicate declaration of psci_cpu_on in psci.h and moves the constants for the system level implementation of the generic timer from arch_helpers.h to arch.h. All other architectural constants are defined in arch.h so there is no need to add them to arch_helpers.h Change-Id: Ia8ad3f91854f7e57fce31873773eede55c384ff1
2013-12-05psci: fix error due to a non zero context idAchin Gupta
In the previous psci implementation, the psci_afflvl_power_on_finish() function would run into an error condition if the value of the context id parameter in the cpu_on and cpu_suspend psci calls was != 0. The parameter was being restored as the return value of the affinity level 0 finisher function. A non zero context id would be treated as an error condition. This would prevent successful wake up of the cpu from a power down state. Also, the contents of the general purpose registers were not being cleared upon return to the non-secure world after a cpu power up. This could potentially allow the non-secure world to view secure data. This patch ensures that all general purpose registers are set to ~0 prior to the final eret that drops the execution to the non-secure world. The context id is used to initialize the general purpose register x0 prior to re-entry into the non-secure world and is no longer restored as a function return value. A platform helper (platform_get_stack()) has been introduced to facilitate this change. Change-Id: I2454911ffd75705d6aa8609a5d250d9b26fa097c
2013-12-05psci: fix values of incorrectly defined constantsAchin Gupta
This patch fixes the following constant values in the psci.h: 1. The affinity level shift value in the power_state parameter of the cpu_suspend psci call. The previous value was preventing shutdown of the affinity level 1. 2. The values used for affinity state constants (ON, OFF, ON_PENDING). They did not match the values expected to be returned by the affinity_info psci api as mentioned in the spec. 3. The state id shift value in the power_state parameter of the cpu_suspend psci call. Change-Id: I62ed5eb0e9640b4aa97b93923d6630e6b877a097
2013-12-05clear wakeup enable bit upon resuming from suspendAchin Gupta
The FVP specific code that gets called after a cpu has been physically powered on after having been turned off or suspended earlier does not clear the PWRC.PWKUPR.WEN bit. Not doing so causes problems if: a cpu is suspended, woken from suspend, powered down through a cpu_off call & receives a spurious interrupt. Since the WEN bit is not cleared after the cpu woke up from suspend, the spurious wakeup will power the cpu on. Since the cpu_off call clears the jump address in the mailbox this spurious wakeup will cause the cpu to crash. This patch fixes this issue by clearing the WEN bit whenever a cpu is powered up. Change-Id: Ic91f5dffe1ed01d76bc7fc807acf0ecd3e38ce5b
2013-12-05rework general purpose registers save and restoreAchin Gupta
The runtime exception handling assembler code used magic numbers for saving and restoring the general purpose register context on stack memory. The memory is interpreted as a 'gp_regs' structure and the magic numbers are offsets to members of this structure. This patch replaces the magic number offsets with constants. It also adds compile time assertions to prevent an incorrect assembler view of this structure. Change-Id: Ibf125bfdd62ba3a33e58c5f1d71f8c229720781c
2013-12-05Enable third party contributionsDan Handley
- Add instructions for contributing to ARM Trusted Firmware. - Update copyright text in all files to acknowledge contributors. Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
2013-12-05Update user guide further to linker scripts changesSandrine Bailleux
This patch updates the user guide section about the memory layout. - Explain the verifications that the linker scripts does on the global memory layout. - Refer to the new linker symbols. - Describe the linker symbols exported to the trusted firmware code. Change-Id: I033ab2b867e8b9776deb4185b9986bcb8218f286
2013-12-05Properly initialise the C runtime environmentSandrine Bailleux
This patch makes sure the C runtime environment is properly initialised before executing any C code. - Zero-initialise NOBITS sections (e.g. the bss section). - Relocate BL1 data from ROM to RAM. Change-Id: I0da81b417b2f0d1f7ef667cc5131b1e47e22571f
2013-12-05Various improvements/cleanups on the linker scriptsSandrine Bailleux
- Check at link-time that bootloader images will fit in memory at run time and that they won't overlap each other. - Remove text and rodata orphan sections. - Define new linker symbols to remove the need for platform setup code to know the order of sections. - Reduce the size of the raw binary images by cutting some sections out of the disk image and allocating them at load time, whenever possible. - Rework alignment constraints on sections. - Remove unused linker symbols. - Homogenize linker symbols names across all BLs. - Add some comments in the linker scripts. Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9
2013-11-27Treat compiler, assembler and linker warnings as errorsSandrine Bailleux
Change-Id: I56284ebf63bef99de1beb4fd86e2d8b6a7962ac0
2013-11-27Generate build products in sub-directoriesJames Morrissey
A single binary can be compiled using a command such as: make CROSS_COMPILE=aarch64-none-elf- bl1 Also make use of brackets consistent in the Makefile. Change-Id: I2180fdb473411ef7cffe39670a7b2de82def812e
2013-11-27Increase default amount of RAM for Base FVPs in FDTsHarry Liebel
- Large RAM-disks may have trouble starting with 2GB of memory. - Increase from 2GB to 4GB in FDT. Change-Id: I12c1b8e5db41114b88c69c48621cb21247a6a6a7
2013-11-27fvp: Remove call to bl2_get_ns_mem_layout() functionSandrine Bailleux
On FVP platforms, for now it is assumed that the normal-world bootloader is already sitting in its final memory location. Therefore, BL2 doesn't need to load it and so it doesn't need to know the extents of the non-trusted DRAM. Change-Id: I33177ab43ca242edc8958f2fa8d994e7cf3e0843
2013-11-27AArch64: Remove EL-agnostic TLB helper functionsSandrine Bailleux
Also, don't invalidate the TLBs in disable_mmu() function, it's better to do it in enable_mmu() function just before actually enabling the MMU. Change-Id: Ib32d6660019b0b2c17254156aad4be67ab4970e1
2013-11-27Unmask SError and Debug exceptions.Sandrine Bailleux
Any asynchronous exception caused by the firmware should be handled in the firmware itself. For this reason, unmask SError exceptions (and Debug ones as well) on all boot paths. Also route external abort and SError interrupts to EL3, otherwise they will target EL1. Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092
2013-11-27fvp: Remove unnecessary initializersSandrine Bailleux
Global and static variables are expected to be initialised to zero by default. This is specified by the C99 standard. This patch removes some unnecessary initialisations of such variables. It fixes a compilation warning at the same time: plat/fvp/bl31_plat_setup.c:82:3: warning: missing braces around initializer [-Wmissing-braces] section("tzfw_coherent_mem"))) = {0}; ^ plat/fvp/bl31_plat_setup.c:82:3: warning: (near initialization for ‘ns_entry_info[0]’) [-Wmissing-braces] Note that GCC should not have emitted this warning message in the first place. The C Standard permits braces to be elided around subaggregate initializers. See this GCC bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119 Change-Id: I13cb0c344feb9803bca8819f976377741fa6bc35
2013-11-27Fix inlining of GIC helper functionsSandrine Bailleux
Change-Id: I27aad560a5da21c0439f3ccc9dc07b026e7c6022
2013-11-27Move generic architectural setup out of blx_plat_arch_setup().Sandrine Bailleux
blx_plat_arch_setup() should only perform platform-specific architectural setup, e.g. enabling the MMU. This patch moves generic architectural setup code out of blx_plat_arch_setup(). Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6
2013-11-14Fix documentation issues in v0.2 releaseJames Morrissey
Change-Id: I4e2a9daa97e3be3d2f53894f2ec7947ba6bb3a16
2013-11-14Add Foundation FVP documentationHarry Liebel
Change-Id: I5e47ba96e128d3a793517441f5a6c9f2ccbdfc66
2013-11-14Add GICv3 ITS to FDTsHarry Liebel
- The interrupt addresses need to be updated to work. Change-Id: Icdd00177095ae9e4eb7b13718762f92e29b1465c
2013-11-14Do not enable CCI on Foundation FVPHarry Liebel
- The Foundation FVP only has one cluster and does not have CCI. Change-Id: If91e81ff72c52e448150089c4cfea3e4d6ae1232
2013-11-14FDTs for v5.2 Foundation modelHarry Liebel
- The Foundation FVP is a cut down version of the Base FVP and as such lacks some components. - Three FDTs are provided. fvp-foundation-gicv2legacy-psci: Use this when setting the Foundation FVP to use GICv2. In this mode the GIC is located at the VE location, as described in the VE platform memory map. fvp-foundation-gicv3-psci : Use this when setting the Foundation FVP to use GICv3. In this mode the GIC is located at the Base location, as described in the Base platform memory map. fvp-foundation-gicv2-psci : Use this when setting the Foundation FVP to use GICv3, but Linux is expected to use GICv2 emulation mode. In this mode the GIC is located at the Base location, but the GICv3 is used in GICv2 emulation mode. Change-Id: I9d69bcef35c64cc8f16550efe077f578e55aaae5
2013-11-14Writing to the FVP LED register should be a 32bit access.Harry Liebel
- Writing to this register with a 64bit access can cause a Systen Error Exception on some models. Change-Id: Ibcf5bdf7ab55707db61c16298f25caff50e1ff7e
2013-10-25ARMv8 Trusted Firmware release v0.2v0.2Achin Gupta