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-rw-r--r--plat/fvp/aarch64/bl1_plat_helpers.S9
-rw-r--r--plat/fvp/aarch64/fvp_common.c2
2 files changed, 2 insertions, 9 deletions
diff --git a/plat/fvp/aarch64/bl1_plat_helpers.S b/plat/fvp/aarch64/bl1_plat_helpers.S
index d72dc39..8cdb10e 100644
--- a/plat/fvp/aarch64/bl1_plat_helpers.S
+++ b/plat/fvp/aarch64/bl1_plat_helpers.S
@@ -226,15 +226,6 @@ platform_cold_boot_init:; .type platform_cold_boot_init, %function
str x19, [x1, x2]
/* ---------------------------------------------
- * Enable CCI-400 for this cluster. No need
- * for locks as no other cpu is active at the
- * moment
- * ---------------------------------------------
- */
- mov x0, x19
- bl cci_enable_coherency
-
- /* ---------------------------------------------
* Architectural init. can be generic e.g.
* enabling stack alignment and platform spec-
* ific e.g. MMU & page table setup as per the
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index 762f542..78a44a5 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -576,6 +576,7 @@ int platform_config_setup(void)
platform_config[CONFIG_MAX_AFF1] = 1;
platform_config[CONFIG_CPU_SETUP] = 0;
platform_config[CONFIG_BASE_MMAP] = 0;
+ platform_config[CONFIG_HAS_CCI] = 0;
break;
case HBI_FVP_BASE:
midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
@@ -587,6 +588,7 @@ int platform_config_setup(void)
platform_config[CONFIG_MAX_AFF0] = 4;
platform_config[CONFIG_MAX_AFF1] = 2;
platform_config[CONFIG_BASE_MMAP] = 1;
+ platform_config[CONFIG_HAS_CCI] = 1;
break;
default:
assert(0);