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-rw-r--r--docs/firmware-design.md13
-rw-r--r--docs/porting-guide.md11
2 files changed, 12 insertions, 12 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index 2bf57ca..8c635a9 100644
--- a/docs/firmware-design.md
+++ b/docs/firmware-design.md
@@ -151,13 +151,6 @@ BL1 performs minimal architectural initialization as follows.
and Advanced SIMD execution are configured to not trap to EL3 by
clearing the `CPTR_EL3.TFP` bit.
- - `CNTFRQ_EL0`. The `CNTFRQ_EL0` register is programmed with the base
- frequency of the system counter, which is retrieved from the first entry
- in the frequency modes table.
-
- - Generic Timer. The system level implementation of the generic timer is
- enabled through the memory mapped interface.
-
#### Platform initialization
BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from
@@ -291,7 +284,8 @@ exception is raised. They implement more elaborate support for handling SMCs
since this is the only mechanism to access the runtime services implemented by
BL3-1 (PSCI for example). BL3-1 checks each SMC for validity as specified by
the [SMC calling convention PDD][SMCCC] before passing control to the required
-SMC handler routine.
+SMC handler routine. BL3-1 programs the `CNTFRQ_EL0` register with the clock
+frequency of the system counter, which is provided by the platform.
#### Platform initialization
@@ -299,7 +293,8 @@ BL3-1 performs detailed platform initialization, which enables normal world
software to function correctly. It also retrieves entrypoint information for
the BL3-3 image loaded by BL2 from the platform defined memory address populated
by BL2. BL3-1 also initializes UART0 (PL011 console), which enables
-access to the `printf` family of functions in BL3-1
+access to the `printf` family of functions in BL3-1. It enables the system
+level implementation of the generic timer through the memory mapped interface.
* GICv2 initialization:
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 56467fb..5dca6fd 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -208,6 +208,13 @@ the implementer chooses. In the ARM FVP port, they are implemented in
platform) & `platform_get_stack()` (to return the base address of that
stack) (see [../plat/common/aarch64/platform_helpers.S]).
+* **Function : uint64_t plat_get_syscnt_freq(void)**
+
+ This function is used by the architecture setup code to retrieve the
+ counter frequency for the CPU's generic timer. This value will be
+ programmed into the `CNTFRQ_EL0` register.
+ In the ARM FVP port, it returns the base frequency of the system counter,
+ which is retrieved from the first entry in the frequency modes table.
2.2 Common optional modifications
---------------------------------
@@ -446,9 +453,6 @@ This function executes with the MMU and data caches enabled. It is responsible
for performing any remaining platform-specific setup that can occur after the
MMU and data cache have been enabled.
-In the ARM FVP port, it zeros out the ZI section and enables the system level
-implementation of the generic timer counter.
-
This function is also responsible for initializing the storage abstraction layer
which is used to load further bootloader images.
@@ -771,6 +775,7 @@ BL3-1 runtime services and normal world software can function correctly.
The ARM FVP port does the following:
* Initializes the generic interrupt controller.
* Configures the CLCD controller.
+* Enables system-level implementation of the generic timer counter.
* Grants access to the system counter timer module
* Initializes the FVP power controller device
* Detects the system topology.