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-rw-r--r--docs/change-log.md3
-rw-r--r--docs/user-guide.md4
2 files changed, 6 insertions, 1 deletions
diff --git a/docs/change-log.md b/docs/change-log.md
index 1f2d12c..61499c7 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -17,6 +17,9 @@ Detailed changes since last release
* Fixed various GCC compiler warnings.
+* Unmask SError and Debug exceptions in the trusted firmware.
+ Also route external abort and SError interrupts to EL3.
+
ARM Trusted Firmware - version 0.2
==================================
diff --git a/docs/user-guide.md b/docs/user-guide.md
index debda44..45e850b 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -661,7 +661,9 @@ BL1 performs minimal architectural initialization as follows.
- `SCR`. Use of the HVC instruction from EL1 is enabled by setting the
`SCR.HCE` bit. FIQ exceptions are configured to be taken in EL3 by
setting the `SCR.FIQ` bit. The register width of the next lower
- exception level is set to AArch64 by setting the `SCR.RW` bit.
+ exception level is set to AArch64 by setting the `SCR.RW` bit. External
+ Aborts and SError Interrupts are configured to be taken in EL3 by
+ setting the `SCR.EA` bit.
- `CPTR_EL3`. Accesses to the `CPACR` from EL1 or EL2, or the `CPTR_EL2`
from EL2 are configured to not trap to EL3 by clearing the